Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication
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| Format: | Preprint |
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2025
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| _version_ | 1866914412544131072 |
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| author | Jaswal, Pragun Krishna, L. Hemanth Srinivasu, B. |
| author_facet | Jaswal, Pragun Krishna, L. Hemanth Srinivasu, B. |
| contents | Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs), designed using energy-efficient positive partial product and negative partial product cells, termed as PPC and NPPC, respectively. The proposed 8-bit exact and approximate PE designs are employed in a 8x8 systolic array, which achieves a energy savings of 22% and 32%, respectively, compared to the existing design. To demonstrate their effectiveness, the proposed PEs are integrated into a systolic array (SA) for Discrete Cosine Transform (DCT) computation, achieving high output quality with a PSNR of 38.21,dB. Furthermore, in an edge detection application using convolution, the approximate PE achieves a PSNR of 30.45,dB. These results highlight the potential of the proposed design to deliver significant energy efficiency while maintaining competitive output quality, making it well-suited for error-resilient image and vision processing applications. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2509_00778 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication Jaswal, Pragun Krishna, L. Hemanth Srinivasu, B. Hardware Architecture Computer Vision and Pattern Recognition Machine Learning Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs), designed using energy-efficient positive partial product and negative partial product cells, termed as PPC and NPPC, respectively. The proposed 8-bit exact and approximate PE designs are employed in a 8x8 systolic array, which achieves a energy savings of 22% and 32%, respectively, compared to the existing design. To demonstrate their effectiveness, the proposed PEs are integrated into a systolic array (SA) for Discrete Cosine Transform (DCT) computation, achieving high output quality with a PSNR of 38.21,dB. Furthermore, in an edge detection application using convolution, the approximate PE achieves a PSNR of 30.45,dB. These results highlight the potential of the proposed design to deliver significant energy efficiency while maintaining competitive output quality, making it well-suited for error-resilient image and vision processing applications. |
| title | Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication |
| topic | Hardware Architecture Computer Vision and Pattern Recognition Machine Learning |
| url | https://arxiv.org/abs/2509.00778 |