Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography
Fuente:
arXiv
Saved in:
| Main Authors: | Baidya, Paresh, Paul, Rourab, Srivastava, Vikas, Debnath, Sumit Kumar |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
by: Baidya, Paresh, et al.
Published: (2022)
by: Baidya, Paresh, et al.
Published: (2022)
Energy-Efficient NTT Sampler for Kyber Benchmarked on FPGA
by: Baidya, Paresh, et al.
Published: (2025)
by: Baidya, Paresh, et al.
Published: (2025)
Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026)
by: Paul, Rourab, et al.
Published: (2026)
Efficient Layered New Bit-Flipping QC-MDPC Decoder for BIKE Post-Quantum Cryptography
by: Cai, Jiaxuan, et al.
Published: (2024)
by: Cai, Jiaxuan, et al.
Published: (2024)
Lightweight Fault Detection Architecture for NTT on FPGA
by: Paul, Rourab, et al.
Published: (2025)
by: Paul, Rourab, et al.
Published: (2025)
High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)
by: Amael, Joshua Tito, et al.
Published: (2024)
CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing
by: Zhang, Jingyao, et al.
Published: (2025)
by: Zhang, Jingyao, et al.
Published: (2025)
RejSCore: Rejection Sampling Core for Multivariate-based Public key Cryptography
by: Imran, Malik, et al.
Published: (2025)
by: Imran, Malik, et al.
Published: (2025)
Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025)
by: Malik, Arsalan Ali
Published: (2025)
REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)
by: Baddour, Yazan, et al.
Published: (2025)
Logistic Map Pseudo Random Number Generator in FPGA
by: Calderon, Mateo Jalen Andrew, et al.
Published: (2024)
by: Calderon, Mateo Jalen Andrew, et al.
Published: (2024)
FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
by: Xu, Zhihan, et al.
Published: (2025)
by: Xu, Zhihan, et al.
Published: (2025)
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs
by: Butt, Shahzad Ahmad, et al.
Published: (2024)
by: Butt, Shahzad Ahmad, et al.
Published: (2024)
Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
by: Kumari, Ruby, et al.
Published: (2025)
by: Kumari, Ruby, et al.
Published: (2025)
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography
by: Tan, Weihang, et al.
Published: (2021)
by: Tan, Weihang, et al.
Published: (2021)
Blockchain-Envisioned Post-Quantum Secure Sanitizable Signature for Audit Logs Management
by: Srivastava, Vikas, et al.
Published: (2023)
by: Srivastava, Vikas, et al.
Published: (2023)
PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems
by: Swaroopa, Sneha, et al.
Published: (2025)
by: Swaroopa, Sneha, et al.
Published: (2025)
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)
by: Zoni, Davide, et al.
Published: (2024)
A High Performance and Efficient Post-Quantum Crypto-Processor for FrodoKEM
by: Li, Kai, et al.
Published: (2026)
by: Li, Kai, et al.
Published: (2026)
NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP Redaction
by: Das, Voktho, et al.
Published: (2026)
by: Das, Voktho, et al.
Published: (2026)
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
by: Pham, Anh Kiet, et al.
Published: (2026)
by: Pham, Anh Kiet, et al.
Published: (2026)
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2022)
by: Olgun, Ataberk, et al.
Published: (2022)
History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services
by: Nakano, Hiroshi, et al.
Published: (2025)
by: Nakano, Hiroshi, et al.
Published: (2025)
ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
by: Kvalsvik, Amund Bergland, et al.
Published: (2025)
by: Kvalsvik, Amund Bergland, et al.
Published: (2025)
Understanding the Error Sensitivity of Privacy-Aware Computing
by: Mazzanti, Matías, et al.
Published: (2025)
by: Mazzanti, Matías, et al.
Published: (2025)
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)
by: Liu, Yuntao, et al.
Published: (2023)
PoSyn: Secure Power Side-Channel Aware Synthesis
by: Srivastava, Amisha, et al.
Published: (2025)
by: Srivastava, Amisha, et al.
Published: (2025)
Memory DisOrder: Memory Re-orderings as a Timerless Side-channel
by: Siddens, Sean, et al.
Published: (2026)
by: Siddens, Sean, et al.
Published: (2026)
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation
by: Qureshi, Moinuddin, et al.
Published: (2024)
by: Qureshi, Moinuddin, et al.
Published: (2024)
Design high-confidence computers using trusted instructional set architecture and emulators
by: Wang, Shuangbao Paul
Published: (2025)
by: Wang, Shuangbao Paul
Published: (2025)
Attacking AI Accelerators by Leveraging Arithmetic Properties of Addition
by: Heidary, Masoud, et al.
Published: (2026)
by: Heidary, Masoud, et al.
Published: (2026)
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection
by: Rostami, Mohamadreza, et al.
Published: (2024)
by: Rostami, Mohamadreza, et al.
Published: (2024)
SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
by: Saravanan, Raghul, et al.
Published: (2025)
by: Saravanan, Raghul, et al.
Published: (2025)
ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits
by: Sekanina, Lukas, et al.
Published: (2026)
by: Sekanina, Lukas, et al.
Published: (2026)
Empowering Malware Detection Efficiency within Processing-in-Memory Architecture
by: Kasarapu, Sreenitha, et al.
Published: (2024)
by: Kasarapu, Sreenitha, et al.
Published: (2024)
ALLMod: Exploring $\underline{\mathbf{A}}$rea-Efficiency of $\underline{\mathbf{L}}$UT-based $\underline{\mathbf{L}}$arge Number $\underline{\mathbf{Mod}}$ular Reduction via Hybrid Workloads
by: Liu, Fangxin, et al.
Published: (2025)
by: Liu, Fangxin, et al.
Published: (2025)
DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
by: Hassan, Muhammad, et al.
Published: (2025)
by: Hassan, Muhammad, et al.
Published: (2025)
Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)
by: Mashburn, Joshua, et al.
Published: (2025)
FastFlow in FPGA Stacks of Data Centers
by: Paul, Rourab, et al.
Published: (2024)
by: Paul, Rourab, et al.
Published: (2024)
Descriptor-Based Object-Aware Memory Systems: A Comprehensive Review
by: Tong, Dong
Published: (2025)
by: Tong, Dong
Published: (2025)
Similar Items
-
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
by: Baidya, Paresh, et al.
Published: (2022) -
Energy-Efficient NTT Sampler for Kyber Benchmarked on FPGA
by: Baidya, Paresh, et al.
Published: (2025) -
Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026) -
Efficient Layered New Bit-Flipping QC-MDPC Decoder for BIKE Post-Quantum Cryptography
by: Cai, Jiaxuan, et al.
Published: (2024) -
Lightweight Fault Detection Architecture for NTT on FPGA
by: Paul, Rourab, et al.
Published: (2025)