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| Autore principale: | |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| Soggetti: | |
| Accesso online: | https://arxiv.org/abs/2509.05636 |
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| _version_ | 1866908522378166272 |
|---|---|
| author | Zhang, Yi |
| author_facet | Zhang, Yi |
| contents | This paper presents a differential 10-bit 2 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a precision-improvement technique. The proposed method breaks the direct tradeoff between the capacitive digital-to-analog converter (CDAC) units and the resolution of SAR ADCs by extending the effective input range, thereby enhancing the effective number of bits (ENOB). Specifically, the technique is implemented by switching the potential of the MSB capacitors during the sampling phase. Theoretically, it enables a precision improvement of more than 0.5-bit. In this design, 512 capacitor units and a reference voltage VREF are employed, achieving an extended input range of +-1.5VREF and an equivalent resolution of 10.5-bit. Fabricated in a 180-nm CMOS process, the prototype chip demonstrates 10.36-bit ENOB in post-simulation, while consuming 48μW at a sampling rate of 2 MS/s under a 1.8-V supply, with an area of 0.79mm2. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_05636 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A 10-bit SAR ADC with 1.5x Input Range Zhang, Yi Applied Physics This paper presents a differential 10-bit 2 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a precision-improvement technique. The proposed method breaks the direct tradeoff between the capacitive digital-to-analog converter (CDAC) units and the resolution of SAR ADCs by extending the effective input range, thereby enhancing the effective number of bits (ENOB). Specifically, the technique is implemented by switching the potential of the MSB capacitors during the sampling phase. Theoretically, it enables a precision improvement of more than 0.5-bit. In this design, 512 capacitor units and a reference voltage VREF are employed, achieving an extended input range of +-1.5VREF and an equivalent resolution of 10.5-bit. Fabricated in a 180-nm CMOS process, the prototype chip demonstrates 10.36-bit ENOB in post-simulation, while consuming 48μW at a sampling rate of 2 MS/s under a 1.8-V supply, with an area of 0.79mm2. |
| title | A 10-bit SAR ADC with 1.5x Input Range |
| topic | Applied Physics |
| url | https://arxiv.org/abs/2509.05636 |