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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2509.06289 |
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| _version_ | 1866916939318689792 |
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| author | Wei, Shaoqi Wang, Senling Kai, Hiroshi Higami, Yoshinobu Ma, Ruijun Ni, Tianming Wen, Xiaoqing Takahashi, Hiroshi |
| author_facet | Wei, Shaoqi Wang, Senling Kai, Hiroshi Higami, Yoshinobu Ma, Ruijun Ni, Tianming Wen, Xiaoqing Takahashi, Hiroshi |
| contents | Silent Data Errors (SDEs) from time-zero defects and aging degrade safety-critical systems. Functional testing detects SDE-related faults but is expensive to simulate. We present a unified spatio-temporal graph convolutional network (ST-GCN) for fast, accurate prediction of long-cycle fault impact probabilities (FIPs) in large sequential circuits, supporting quantitative risk assessment. Gate-level netlists are modeled as spatio-temporal graphs to capture topology and signal timing; dedicated spatial and temporal encoders predict multi-cycle FIPs efficiently. On ISCAS-89 benchmarks, the method reduces simulation time by more than 10x while maintaining high accuracy (mean absolute error 0.024 for 5-cycle predictions). The framework accepts features from testability metrics or fault simulation, allowing efficiency-accuracy trade-offs. A test-point selection study shows that choosing observation points by predicted FIPs improves detection of long-cycle, hard-to-detect faults. The approach scales to SoC-level test strategy optimization and fits downstream electronic design automation flows. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_06289 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults Wei, Shaoqi Wang, Senling Kai, Hiroshi Higami, Yoshinobu Ma, Ruijun Ni, Tianming Wen, Xiaoqing Takahashi, Hiroshi Machine Learning Hardware Architecture Emerging Technologies B.7.3 Silent Data Errors (SDEs) from time-zero defects and aging degrade safety-critical systems. Functional testing detects SDE-related faults but is expensive to simulate. We present a unified spatio-temporal graph convolutional network (ST-GCN) for fast, accurate prediction of long-cycle fault impact probabilities (FIPs) in large sequential circuits, supporting quantitative risk assessment. Gate-level netlists are modeled as spatio-temporal graphs to capture topology and signal timing; dedicated spatial and temporal encoders predict multi-cycle FIPs efficiently. On ISCAS-89 benchmarks, the method reduces simulation time by more than 10x while maintaining high accuracy (mean absolute error 0.024 for 5-cycle predictions). The framework accepts features from testability metrics or fault simulation, allowing efficiency-accuracy trade-offs. A test-point selection study shows that choosing observation points by predicted FIPs improves detection of long-cycle, hard-to-detect faults. The approach scales to SoC-level test strategy optimization and fits downstream electronic design automation flows. |
| title | A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults |
| topic | Machine Learning Hardware Architecture Emerging Technologies B.7.3 |
| url | https://arxiv.org/abs/2509.06289 |