Dato: A Task-Based Programming Model for Dataflow Accelerators
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arXiv
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| Autores principales: | , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866909776160489472 |
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| author | Fang, Shihan Chen, Hongzheng Zhang, Niansong Li, Jiajie Meng, Han Liu, Adrian Zhang, Zhiru |
| author_facet | Fang, Shihan Chen, Hongzheng Zhang, Niansong Li, Jiajie Meng, Han Liu, Adrian Zhang, Zhiru |
| contents | Recent deep learning workloads increasingly push computational demand beyond what current memory systems can sustain, with many kernels stalling on data movement rather than computation. While modern dataflow accelerators incorporate on-chip streaming to mitigate off-chip bandwidth limitations, existing programming models struggle to harness these capabilities effectively. Low-level interfaces provide fine-grained control but impose significant development overhead, whereas high-level tile-based languages abstract away communication details, restricting optimization and forcing compilers to reconstruct the intended dataflow. We present Dato, a Python-embedded, task-based programming model for dataflow accelerators that elevates data communication and sharding to first-class type constructs. Developers write programs as a graph of tasks connected via explicit stream types, with sharded inputs specified using layout types. These tasks are first mapped virtually onto the accelerator's spatial fabric, and the compiler then generates a physical mapping that respects hardware constraints. Experimental results on both AMD Ryzen AI NPU and Alveo FPGA devices demonstrate that Dato achieves high performance while significantly reducing the burden of writing optimized code. On the NPU, Dato attains up to 84% hardware utilization for GEMM and delivers a 2.81x speedup on attention kernels compared to a state-of-the-art commercial framework. On the FPGA, Dato surpasses leading frameworks in performance when generating custom systolic arrays, achieving 98% of the theoretical peak performance. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_06794 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Dato: A Task-Based Programming Model for Dataflow Accelerators Fang, Shihan Chen, Hongzheng Zhang, Niansong Li, Jiajie Meng, Han Liu, Adrian Zhang, Zhiru Programming Languages Hardware Architecture Machine Learning Recent deep learning workloads increasingly push computational demand beyond what current memory systems can sustain, with many kernels stalling on data movement rather than computation. While modern dataflow accelerators incorporate on-chip streaming to mitigate off-chip bandwidth limitations, existing programming models struggle to harness these capabilities effectively. Low-level interfaces provide fine-grained control but impose significant development overhead, whereas high-level tile-based languages abstract away communication details, restricting optimization and forcing compilers to reconstruct the intended dataflow. We present Dato, a Python-embedded, task-based programming model for dataflow accelerators that elevates data communication and sharding to first-class type constructs. Developers write programs as a graph of tasks connected via explicit stream types, with sharded inputs specified using layout types. These tasks are first mapped virtually onto the accelerator's spatial fabric, and the compiler then generates a physical mapping that respects hardware constraints. Experimental results on both AMD Ryzen AI NPU and Alveo FPGA devices demonstrate that Dato achieves high performance while significantly reducing the burden of writing optimized code. On the NPU, Dato attains up to 84% hardware utilization for GEMM and delivers a 2.81x speedup on attention kernels compared to a state-of-the-art commercial framework. On the FPGA, Dato surpasses leading frameworks in performance when generating custom systolic arrays, achieving 98% of the theoretical peak performance. |
| title | Dato: A Task-Based Programming Model for Dataflow Accelerators |
| topic | Programming Languages Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2509.06794 |