:: Library Catalog

Image de couverture de livre

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Ifrim, Rares, Popescu, Decebal
Format:	Preprint
Publié:	2025
Sujets:	Hardware Architecture
Accès en ligne:	https://arxiv.org/abs/2509.08067
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
par: Qin, Kun, et autres
Publié: (2025)

SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
par: Brignone, Giovanni, et autres
Publié: (2024)

FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
par: Ranjbar, Ali, et autres
Publié: (2025)

Stream-HLS: Towards Automatic Dataflow Acceleration
par: Basalama, Suhail, et autres
Publié: (2025)

A Novel FPGA-based CNN Hardware Accelerator: Optimization for Convolutional Layers using Karatsuba Ofman Multiplier
par: Sarkar, Amit
Publié: (2024)

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
par: Zou, Qingyun, et autres
Publié: (2025)

MING: An Automated CNN-to-Edge MLIR HLS framework
par: Bi, Jiahong, et autres
Publié: (2026)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
par: Yin, Shuo, et autres
Publié: (2026)

Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
par: Kumari, Ruby, et autres
Publié: (2025)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
par: Liu, Shang, et autres
Publié: (2025)

A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation
par: Lei, Jie, et autres
Publié: (2025)

SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS
par: Shi, Rui, et autres
Publié: (2025)

Exploring FPGA designs for MX and beyond
par: Samson, Ebby, et autres
Publié: (2024)

FormalRTL: Verified RTL Synthesis at Scale
par: Li, Kezhi, et autres
Publié: (2026)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
par: Li, Runkai, et autres
Publié: (2025)

SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator
par: Wang, Peipei, et autres
Publié: (2025)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
par: Böttcher, Andreas, et autres
Publié: (2024)

AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
par: Ahmed, Md Rubel, et autres
Publié: (2024)

Iceberg: Enhancing HLS Modeling with Synthetic Data
par: Ding, Zijian, et autres
Publié: (2025)

Extend IVerilog to Support Batch RTL Fault Simulation
par: Tang, Jiaping, et autres
Publié: (2025)

GSIM: Accelerating RTL Simulation for Large-Scale Designs
par: Chen, Lu, et autres
Publié: (2025)

UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
par: Zuo, Dongsheng, et autres
Publié: (2024)

R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges
par: Metz, David, et autres
Publié: (2024)

DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
par: Metz, David, et autres
Publié: (2026)

ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
par: Deng, Chenhui, et autres
Publié: (2026)

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
par: Li, Chengxi, et autres
Publié: (2025)

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
par: Sehm, Robin, et autres
Publié: (2025)

RTL Verification for Secure Speculation Using Contract Shadow Logic
par: Tan, Qinhan, et autres
Publié: (2024)

ROVER: RTL Optimization via Verified E-Graph Rewriting
par: Coward, Samuel, et autres
Publié: (2024)

UVLLM: An Automated Universal RTL Verification Framework using LLMs
par: Hu, Yuchen, et autres
Publié: (2024)

ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools
par: Wanna, Andy, et autres
Publié: (2025)

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
par: Allam, Ahmed, et autres
Publié: (2024)

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
par: Fang, Wenji, et autres
Publié: (2026)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
par: Tang, Jiaping, et autres
Publié: (2025)

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
par: Tsai, Yun-Da, et autres
Publié: (2023)

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
par: Emami, Mahyar, et autres
Publié: (2023)

Efficient Task Transfer for HLS DSE
par: Ding, Zijian, et autres
Publié: (2024)

Efficient Multi-Cycle Folded Integer Multipliers
par: Houraniah, Ahmad, et autres
Publié: (2023)

MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
par: Chaurasia, Ansh
Publié: (2025)

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
par: Qi, Haomin, et autres
Publié: (2025)