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| Main Authors: | , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2509.09505 |
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| _version_ | 1866911585764638720 |
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| author | Wu, Haoran Xiao, Can Nie, Jiayi Guo, Xuan Lou, Binglei Wong, Jeffrey T. H. Mo, Zhiwen Zhang, Cheng Forys, Przemyslaw Ai, Chengyang Adeniran, Timi Luk, Wayne Fan, Hongxiang Cheng, Jianyi Jones, Timothy M. Antonova, Rika Mullins, Robert Zhao, Aaron |
| author_facet | Wu, Haoran Xiao, Can Nie, Jiayi Guo, Xuan Lou, Binglei Wong, Jeffrey T. H. Mo, Zhiwen Zhang, Cheng Forys, Przemyslaw Ai, Chengyang Adeniran, Timi Luk, Wayne Fan, Hongxiang Cheng, Jianyi Jones, Timothy M. Antonova, Rika Mullins, Robert Zhao, Aaron |
| contents | LLMs now form the backbone of AI agents across a diverse range of applications, including tool use, command-line interfaces, and web or computer interaction. These agentic LLM inference tasks are fundamentally different from chatbot-focused inference. They often involve much longer context lengths to capture complex and prolonged inputs, such as an entire webpage DOM or complicated tool-call trajectories. This, in turn, generates significant off-chip memory traffic during inference and causes workloads to be constrained by two memory walls, namely the bandwidth wall and the capacity wall, preventing compute units from achieving high utilization.
In this paper, we introduce PLENA, a hardware-software co-designed system built around three core optimization pathways. PLENA features a novel flattened systolic-array architecture (Pathway 1) and efficient compute and memory units that support an asymmetric quantization scheme (Pathway 2). It also provides native support for FlashAttention (Pathway 3). In addition, PLENA includes a complete software-hardware stack, consisting of a custom ISA, a compiler, a transaction-level simulator, and an automated design-space exploration flow. Experimental results show that PLENA delivers up to 2.23x and 4.70x higher throughput than the A100 GPU and TPU v6e, respectively, under identical multiplier counts and memory configurations during LLaMA agentic inference. PLENA also achieves up to 4.04x higher energy efficiency than the A100 GPU. The full PLENA system, including its simulator, compiler, ISA, and RTL implementation, will be open-sourced to the research community. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_09505 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference Wu, Haoran Xiao, Can Nie, Jiayi Guo, Xuan Lou, Binglei Wong, Jeffrey T. H. Mo, Zhiwen Zhang, Cheng Forys, Przemyslaw Ai, Chengyang Adeniran, Timi Luk, Wayne Fan, Hongxiang Cheng, Jianyi Jones, Timothy M. Antonova, Rika Mullins, Robert Zhao, Aaron Hardware Architecture LLMs now form the backbone of AI agents across a diverse range of applications, including tool use, command-line interfaces, and web or computer interaction. These agentic LLM inference tasks are fundamentally different from chatbot-focused inference. They often involve much longer context lengths to capture complex and prolonged inputs, such as an entire webpage DOM or complicated tool-call trajectories. This, in turn, generates significant off-chip memory traffic during inference and causes workloads to be constrained by two memory walls, namely the bandwidth wall and the capacity wall, preventing compute units from achieving high utilization. In this paper, we introduce PLENA, a hardware-software co-designed system built around three core optimization pathways. PLENA features a novel flattened systolic-array architecture (Pathway 1) and efficient compute and memory units that support an asymmetric quantization scheme (Pathway 2). It also provides native support for FlashAttention (Pathway 3). In addition, PLENA includes a complete software-hardware stack, consisting of a custom ISA, a compiler, a transaction-level simulator, and an automated design-space exploration flow. Experimental results show that PLENA delivers up to 2.23x and 4.70x higher throughput than the A100 GPU and TPU v6e, respectively, under identical multiplier counts and memory configurations during LLaMA agentic inference. PLENA also achieves up to 4.04x higher energy efficiency than the A100 GPU. The full PLENA system, including its simulator, compiler, ISA, and RTL implementation, will be open-sourced to the research community. |
| title | Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2509.09505 |