MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness
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arXiv
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| Main Authors: | Wang, Huizheng, Wang, Zichuan, Yue, Zhiheng, Long, Yousheng, Wei, Taiquan, Yang, Jianxun, Wang, Yang, Li, Chao, Wei, Shaojun, Hu, Yang, Yin, Shouyi |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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