:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Xu, Tiancheng, Cox, Alan L., Rixner, Scott
Format:	Preprint
Published:	2025
Subjects:	Numerical Analysis Hardware Architecture
Online Access:	https://arxiv.org/abs/2509.10934
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Efficient FRW Transitions via Stochastic Finite Differences for Handling Non-Stratified Dielectrics
by: Huang, Jiechen, et al.
Published: (2025)

Bit-Accurate Modeling of GPU Matrix Multiply-Accumulate Units: Demystifying Numerical Discrepancy and Accuracy
by: Xie, Peichen, et al.
Published: (2025)

Accurate Models of NVIDIA Tensor Cores
by: Khattak, Faizan A., et al.
Published: (2025)

Accurate Block Quantization in LLMs with Outliers
by: Trukhanov, Nikita, et al.
Published: (2024)

MATLAB Simulator of Level-Index Arithmetic
by: Mikaitis, Mantas
Published: (2024)

Mixed-precision finite element kernels and assembly: Rounding error analysis and hardware acceleration
by: Croci, M., et al.
Published: (2024)

An Open-Source Framework for Efficient Numerically-Tailored Computations
by: Ledoux, Louis, et al.
Published: (2024)

Hawkeye: Reproducing GPU-Level Non-Determinism
by: Badash, Erez, et al.
Published: (2026)

A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion
by: Giamouzis, Christos, et al.
Published: (2024)

MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits
by: Garyfallou, Dimitrios, et al.
Published: (2023)

eXmY: A Data Type and Technique for Arbitrary Bit Precision Quantization
by: Agrawal, Aditya, et al.
Published: (2024)

Efficient Hardware Accelerator Based on Medium Granularity Dataflow for SpTRSV
by: Chen, Qian, et al.
Published: (2024)

SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Tracking
by: Ghanta, Susmita, et al.
Published: (2026)

TREA: Low-precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
by: Sharma, Vijay Pratap, et al.
Published: (2026)

An SMT Formalization of Mixed-Precision Matrix Multiplication: Modeling Three Generations of Tensor Cores
by: Valpey, Benjamin, et al.
Published: (2025)

EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
by: Lokhande, Mukul, et al.
Published: (2026)

Regular mixed-radix DFT matrix factorization for in-place FFT accelerators
by: Salishev, Sergey
Published: (2025)

HYLU: Hybrid Parallel Sparse LU Factorization
by: Chen, Xiaoming
Published: (2025)

AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs
by: Lyu, Hongqin, et al.
Published: (2025)

DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specifications
by: Wang, Yonghao, et al.
Published: (2025)

AssertFix: Empowering Automated Assertion Fix via Large Language Models
by: Lyu, Hongqin, et al.
Published: (2025)

Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems
by: Elgamal, Mariam, et al.
Published: (2025)

Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
by: Böttcher, Andreas, et al.
Published: (2024)

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
by: Khadem, Alireza, et al.
Published: (2025)

LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration
by: Vungarala, Deepak, et al.
Published: (2025)

Hardware-Software Co-Design for Accelerating Transformer Inference Leveraging Compute-in-Memory
by: Kim, Dong Eun, et al.
Published: (2025)

Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design
by: Andrulis, Tanner, et al.
Published: (2024)

Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations
by: Mohammad, Sakib, et al.
Published: (2024)

AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging
by: Lyu, Hongqin, et al.
Published: (2025)

Disaggregated Architectures and the Redesign of Data Center Ecosystems: Scheduling, Pooling, and Infrastructure Trade-offs
by: Guo, Chao, et al.
Published: (2025)

Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration
by: Du, Shuting, et al.
Published: (2025)

ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing
by: Vlcek, Ondrej, et al.
Published: (2025)

Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference
by: Wang, Xinyu, et al.
Published: (2026)

Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
by: Galimberti, Andrea, et al.
Published: (2024)

A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing
by: Chowdhury, Md Rownak Hossain, et al.
Published: (2026)

Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification
by: Wang, Yonghao, et al.
Published: (2026)

CoQMoE: Co-Designed Quantization and Computation Orchestration for Mixture-of-Experts Vision Transformer on FPGA
by: Dong, Jiale, et al.
Published: (2025)

Architecting Scalable Trapped Ion Quantum Computers using Surface Codes
by: Jones, Scott, et al.
Published: (2025)

Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
by: Malhotra, Akul, et al.
Published: (2025)

Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design
by: Ai, Chenyang, et al.
Published: (2026)