always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866918140722544640 |
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| author | Parthasarathy, Rishab Attaluri, Akshay Ting, Gilford |
| author_facet | Parthasarathy, Rishab Attaluri, Akshay Ting, Gilford |
| contents | We present a design for an extensible video conferencing stack implemented entirely in hardware on a Nexys4 DDR FPGA, which uses the M-JPEG codec to compress video and a UDP networking stack to communicate between the FPGA and the receiving computer. This networking stack accepts real-time updates from both the video codec and the audio controller, which means that video will be able to be streamed at 30 FPS from the FPGA to a computer. On the computer side, a Python script reads the Ethernet packets and decodes the packets into the video and the audio for real time playback. We evaluate this architecture using both functional, simulation-driven verification in Cocotb and by synthesizing SystemVerilog RTL code using Vivado for deployment on our Nexys4 DDR FPGA, where we evaluate both end-to-end latency and throughput of video transmission. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_11503 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission Parthasarathy, Rishab Attaluri, Akshay Ting, Gilford Hardware Architecture We present a design for an extensible video conferencing stack implemented entirely in hardware on a Nexys4 DDR FPGA, which uses the M-JPEG codec to compress video and a UDP networking stack to communicate between the FPGA and the receiving computer. This networking stack accepts real-time updates from both the video codec and the audio controller, which means that video will be able to be streamed at 30 FPS from the FPGA to a computer. On the computer side, a Python script reads the Ethernet packets and decodes the packets into the video and the audio for real time playback. We evaluate this architecture using both functional, simulation-driven verification in Cocotb and by synthesizing SystemVerilog RTL code using Vivado for deployment on our Nexys4 DDR FPGA, where we evaluate both end-to-end latency and throughput of video transmission. |
| title | always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2509.11503 |