Cover Image

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations

Fuente: arXiv

Saved in:

Bibliographic Details
Main Author:	Parthasarathy, Rishab
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission
by: Parthasarathy, Rishab, et al.
Published: (2025)

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration
by: Taka, Endri, et al.
Published: (2025)

FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill
by: Jayanth, Rakshith, et al.
Published: (2026)

FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption
by: Xu, Zhihan, et al.
Published: (2025)

Holistic Optimization Framework for FPGA Accelerators
by: Pouget, Stéphane, et al.
Published: (2025)

Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
by: Li, Jindong, et al.
Published: (2024)

Systolic Array Acceleration of Diagonal-Optimized Sparse-Sparse Matrix Multiplication for Efficient Quantum Simulation
by: Su, Yuchao, et al.
Published: (2025)

Sparse-on-Dense: Area and Energy-Efficient Computing of Sparse Neural Networks on Dense Matrix Multiplication Accelerators
by: Yoon, Hyunsung, et al.
Published: (2026)

GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication
by: Gerami, Armin, et al.
Published: (2024)

A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
by: Petropoulos, Anastasios, et al.
Published: (2025)

Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration
by: Shahawy, Mohamed, et al.
Published: (2025)

Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators
by: Mecik, Michael, et al.
Published: (2025)

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
by: Masar, Filip, et al.
Published: (2025)

SpecMamba: Accelerating Mamba Inference on FPGA with Speculative Decoding
by: Zhong, Linfeng, et al.
Published: (2025)

A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
by: Yunusoglu, Aybars, et al.
Published: (2026)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025)

An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
by: Ferry, Corentin, et al.
Published: (2024)

A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow
by: Zhao, Zhiyuan, et al.
Published: (2024)

SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization
by: Versluis, Manno, et al.
Published: (2025)

LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
by: Di, Zhixiong, et al.
Published: (2023)

Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA
by: Li, Jindong, et al.
Published: (2025)

Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA
by: Ando, Takuto, et al.
Published: (2025)

SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator
by: Wang, Peipei, et al.
Published: (2025)

Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph Analytics
by: Jaiyeoba, Oluwole, et al.
Published: (2024)

Real-Time, Energy-Efficient, Sampling-Based Optimal Control via FPGA Acceleration
by: Desai, Tanmay, et al.
Published: (2026)

if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs
by: Butt, Shahzad Ahmad, et al.
Published: (2024)

A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
by: Gao, Yizhao, et al.
Published: (2024)

SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
by: Umuroglu, Yaman, et al.
Published: (2025)

FPGA-Optimized Hardware Accelerator for Fast Fourier Transform and Singular Value Decomposition in AI
by: Ding, Hong, et al.
Published: (2025)

Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications
by: Leon, Vasileios, et al.
Published: (2025)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
by: Zhang, Xinmiao, et al.
Published: (2024)

ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation
by: Ruelas-Petrisko, Daniel, et al.
Published: (2025)

ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)

FireFly-P: FPGA-Accelerated Spiking Neural Network Plasticity for Robust Adaptive Control
by: Li, Tenglong, et al.
Published: (2026)

FPGA-Based Neural Network Accelerators for Space Applications: A Survey
by: Antunes, Pedro, et al.
Published: (2025)

An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT
by: Shao, Haikuo, et al.
Published: (2024)

FPPS: An FPGA-Based Point Cloud Processing System
by: Zhou, Xiaofeng, et al.
Published: (2026)

Design and Implementation of BNN-Based Object Detection on FPGA
by: Zhao, Xuyu, et al.
Published: (2026)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models
by: Huang, Mingqiang, et al.
Published: (2024)

An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes
by: Wang, Miaoxin, et al.
Published: (2024)