Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization
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arXiv
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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866915497333751808 |
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| author | Ren, Yi Peng, Baokang Xue, Chenhao Guo, Kairong Wang, Yukun Cheng, Guoyao Lin, Yibo Zhang, Lining Sun, Guangyu |
| author_facet | Ren, Yi Peng, Baokang Xue, Chenhao Guo, Kairong Wang, Yukun Cheng, Guoyao Lin, Yibo Zhang, Lining Sun, Guangyu |
| contents | With the diminishing return from Moore's Law, system-technology co-optimization (STCO) has emerged as a promising approach to sustain the scaling trends in the VLSI industry. By bridging the gap between system requirements and technology innovations, STCO enables customized optimizations for application-driven system architectures. However, existing research lacks sufficient discussion on efficient STCO methodologies, particularly in addressing the information gap across design hierarchies and navigating the expansive cross-layer design space. To address these challenges, this paper presents Orthrus, a dual-loop automated framework that synergizes system-level and technology-level optimizations. At the system level, Orthrus employs a novel mechanism to prioritize the optimization of critical standard cells using system-level statistics. It also guides technology-level optimization via the normal directions of the Pareto frontier efficiently explored by Bayesian optimization. At the technology level, Orthrus leverages system-aware insights to optimize standard cell libraries. It employs a neural network-assisted enhanced differential evolution algorithm to efficiently optimize technology parameters. Experimental results on 7nm technology demonstrate that Orthrus achieves 12.5% delay reduction at iso-power and 61.4% power savings at iso-delay over the baseline approaches, establishing new Pareto frontiers in STCO. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_13029 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization Ren, Yi Peng, Baokang Xue, Chenhao Guo, Kairong Wang, Yukun Cheng, Guoyao Lin, Yibo Zhang, Lining Sun, Guangyu Hardware Architecture With the diminishing return from Moore's Law, system-technology co-optimization (STCO) has emerged as a promising approach to sustain the scaling trends in the VLSI industry. By bridging the gap between system requirements and technology innovations, STCO enables customized optimizations for application-driven system architectures. However, existing research lacks sufficient discussion on efficient STCO methodologies, particularly in addressing the information gap across design hierarchies and navigating the expansive cross-layer design space. To address these challenges, this paper presents Orthrus, a dual-loop automated framework that synergizes system-level and technology-level optimizations. At the system level, Orthrus employs a novel mechanism to prioritize the optimization of critical standard cells using system-level statistics. It also guides technology-level optimization via the normal directions of the Pareto frontier efficiently explored by Bayesian optimization. At the technology level, Orthrus leverages system-aware insights to optimize standard cell libraries. It employs a neural network-assisted enhanced differential evolution algorithm to efficiently optimize technology parameters. Experimental results on 7nm technology demonstrate that Orthrus achieves 12.5% delay reduction at iso-power and 61.4% power savings at iso-delay over the baseline approaches, establishing new Pareto frontiers in STCO. |
| title | Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2509.13029 |