Copertina

TENET: An Efficient Sparsity-Aware LUT-Centric Architecture for Ternary LLM Inference On Edge

Fuente: arXiv

Salvato in:

Dettagli Bibliografici
Autori principali:	Huang, Zhirui, Ma, Rui, Cao, Shijie, Shu, Ran, Wang, Ian, Cao, Ting, Chen, Chixiao, Xiong, Yongqiang
Natura:	Preprint
Pubblicazione:	2025
Soggetti:	Hardware Architecture
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

Documenti analoghi

LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs
di: He, Zifan, et al.
Pubblicazione: (2025)

HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference
di: Sun, Chang, et al.
Pubblicazione: (2026)

T-MAN: Enabling End-to-End Low-Bit LLM Inference on NPUs via Unified Table Lookup
di: Wei, Jianyu, et al.
Pubblicazione: (2025)

NVLLM: A 3D NAND-Centric Architecture Enabling Edge on-Device LLM Inference
di: Hao, Mingbo, et al.
Pubblicazione: (2026)

LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference
di: Mo, Zhiwen, et al.
Pubblicazione: (2024)

TerEffic: Highly Efficient Ternary LLM Inference on FPGA
di: Yin, Chenyang, et al.
Pubblicazione: (2025)

TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence
di: Guan, Hongyi, et al.
Pubblicazione: (2026)

LUMINA: LLM-Guided GPU Architecture Exploration via Bottleneck Analysis
di: Zhang, Tao, et al.
Pubblicazione: (2026)

A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network
di: Jiang, Aojie, et al.
Pubblicazione: (2026)

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
di: Pun, Junius, et al.
Pubblicazione: (2025)

LOCALUT: Harnessing Capacity-Computation Tradeoffs for LUT-Based Inference in DRAM-PIM
di: Hong, Junguk, et al.
Pubblicazione: (2026)

Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization
di: Lou, Binglei, et al.
Pubblicazione: (2026)

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
di: Andronic, Marta, et al.
Pubblicazione: (2023)

PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning
di: Andronic, Marta, et al.
Pubblicazione: (2025)

MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness
di: Wang, Huizheng, et al.
Pubblicazione: (2025)

Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decoding
di: Fan, Wang, et al.
Pubblicazione: (2026)

LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference
di: Zheng, Jianing, et al.
Pubblicazione: (2025)

PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs
di: Lou, Binglei, et al.
Pubblicazione: (2024)

VitaLLM: A Versatile, Ultra-Compact Ternary LLM Accelerator with Dependency-Aware Scheduling
di: Lin, Zi-Wei, et al.
Pubblicazione: (2026)

Reimagining Memory Access for LLM Inference: Compression-Aware Memory Controller Design
di: Xie, Rui, et al.
Pubblicazione: (2025)

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
di: Yu, Feng, et al.
Pubblicazione: (2026)

TeLLMe: An Energy-Efficient Ternary LLM Accelerator for Prefilling and Decoding on Edge FPGAs
di: Qiao, Ye, et al.
Pubblicazione: (2025)

SHIELD: A Segmented Hierarchical Memory Architecture for Energy-Efficient LLM Inference on Edge NPUs
di: Zhang, Jintao, et al.
Pubblicazione: (2026)

Mapping Space Exploration for Multi-Chiplet Accelerators Targeting LLM Inference Serving Workloads
di: Li, Boyu, et al.
Pubblicazione: (2025)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
di: Duan, Cenlin, et al.
Pubblicazione: (2024)

Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads
di: Khabbazan, Bahareh, et al.
Pubblicazione: (2025)

xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems
di: Rutishauser, Georg, et al.
Pubblicazione: (2024)

LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator
di: Li, Guoyu, et al.
Pubblicazione: (2025)

SAL-PIM: A Subarray-level Processing-in-Memory Architecture with LUT-based Linear Interpolation for Transformer-based Text Generation
di: Han, Wontak, et al.
Pubblicazione: (2024)

PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation
di: Zhang, Wenlun, et al.
Pubblicazione: (2024)

TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees
di: Khataei, Alireza, et al.
Pubblicazione: (2025)

Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
di: Yu, Zhongkai, et al.
Pubblicazione: (2024)

HillInfer: Efficient Long-Context LLM Inference on the Edge with Hierarchical KV Eviction using SmartSSD
di: Sun, He, et al.
Pubblicazione: (2026)

CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the Edge
di: Tian, Chunlin, et al.
Pubblicazione: (2025)

A Survey on LUT-based Deep Neural Networks Implemented in FPGAs
di: Guo, Zeyu
Pubblicazione: (2025)

RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization with Knowledge-infused Reinforcement Learning
di: Cao, Weidong, et al.
Pubblicazione: (2024)

SATA: Sparsity-Aware Scheduling for Selective Token Attention
di: Fan, Zhenkun, et al.
Pubblicazione: (2026)

LP-Spec: Leveraging LPDDR PIM for Efficient LLM Mobile Speculative Inference with Architecture-Dataflow Co-Optimization
di: He, Siyuan, et al.
Pubblicazione: (2025)

VitaLLM: A Versatile and Tiny Accelerator for Mixed-Precision LLM Inference on Edge Devices
di: Lin, Zi-Wei, et al.
Pubblicazione: (2026)

A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks
di: Yi, Zhiqiang, et al.
Pubblicazione: (2025)