How to Identify Suitable Gate Dielectrics for Transistors based on Two-Dimensional Semiconductors
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arXiv
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| Auteurs principaux: | , , , , , , , , , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866909804365086720 |
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| author | Knobloch, Theresia Smets, Quentin Persson, Anton E. O. Khakbaz, Pedram Wilhelmer, Christoph Lin, Dennis Han, Zherui Chung, Yunyan OBrien, Kevin P. Dorow, Chelsey OCoileain, Cormac Lanza, Mario Waldhoer, Dominic Karl, Alexander Liu, Kailang Zhai, Tianyou Peng, Hailin Tan, Congwei Wang, Xiao Renshaw Duesberg, Georg S. Robertson, John Avci, Uygar Radu, Iuliana Pop, Eric de la Rosa, Cesar J. Lockhart Grasser, Tibor |
| author_facet | Knobloch, Theresia Smets, Quentin Persson, Anton E. O. Khakbaz, Pedram Wilhelmer, Christoph Lin, Dennis Han, Zherui Chung, Yunyan OBrien, Kevin P. Dorow, Chelsey OCoileain, Cormac Lanza, Mario Waldhoer, Dominic Karl, Alexander Liu, Kailang Zhai, Tianyou Peng, Hailin Tan, Congwei Wang, Xiao Renshaw Duesberg, Georg S. Robertson, John Avci, Uygar Radu, Iuliana Pop, Eric de la Rosa, Cesar J. Lockhart Grasser, Tibor |
| contents | The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a fundamental challenge, as the dielectric/channel interface dramatically impacts virtually all performance parameters. While several promising gate dielectrics have recently been reported, the evaluation of their quality and suitability is often fragmentary and focused on selected important performance metrics of the gate stack, such as the capacitive gate control, leakage currents, reliability, and ease of fabrication and integration. However, identifying a suitable gate stack is a complex problem that has not yet been approached systematically. In this perspective, we aim to formulate general criteria for good gate dielectrics. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_20014 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | How to Identify Suitable Gate Dielectrics for Transistors based on Two-Dimensional Semiconductors Knobloch, Theresia Smets, Quentin Persson, Anton E. O. Khakbaz, Pedram Wilhelmer, Christoph Lin, Dennis Han, Zherui Chung, Yunyan OBrien, Kevin P. Dorow, Chelsey OCoileain, Cormac Lanza, Mario Waldhoer, Dominic Karl, Alexander Liu, Kailang Zhai, Tianyou Peng, Hailin Tan, Congwei Wang, Xiao Renshaw Duesberg, Georg S. Robertson, John Avci, Uygar Radu, Iuliana Pop, Eric de la Rosa, Cesar J. Lockhart Grasser, Tibor Applied Physics Mesoscale and Nanoscale Physics The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a fundamental challenge, as the dielectric/channel interface dramatically impacts virtually all performance parameters. While several promising gate dielectrics have recently been reported, the evaluation of their quality and suitability is often fragmentary and focused on selected important performance metrics of the gate stack, such as the capacitive gate control, leakage currents, reliability, and ease of fabrication and integration. However, identifying a suitable gate stack is a complex problem that has not yet been approached systematically. In this perspective, we aim to formulate general criteria for good gate dielectrics. |
| title | How to Identify Suitable Gate Dielectrics for Transistors based on Two-Dimensional Semiconductors |
| topic | Applied Physics Mesoscale and Nanoscale Physics |
| url | https://arxiv.org/abs/2509.20014 |