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| Autores principales: | , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
| Acceso en línea: | https://arxiv.org/abs/2509.20215 |
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| _version_ | 1866912754772738048 |
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| author | Yang, Guang Zheng, Wei Chen, Xiang Sun, Yifan Zhang, Fengji Zhuo, Terry Yue |
| author_facet | Yang, Guang Zheng, Wei Chen, Xiang Sun, Yifan Zhang, Fengji Zhuo, Terry Yue |
| contents | LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_20215 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation Yang, Guang Zheng, Wei Chen, Xiang Sun, Yifan Zhang, Fengji Zhuo, Terry Yue Hardware Architecture Artificial Intelligence Software Engineering LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods. |
| title | The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation |
| topic | Hardware Architecture Artificial Intelligence Software Engineering |
| url | https://arxiv.org/abs/2509.20215 |