:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Ahadi, Soroush, Modarressi, Mehdi, Daneshtalab, Masoud
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture n/a
Online Access:	https://arxiv.org/abs/2509.22512
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

A Customized Memory-aware Architecture for Biological Sequence Alignment
by: Akbari, Nasrin, et al.
Published: (2025)

Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip
by: Zaeemi, Meysam, et al.
Published: (2026)

DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network
by: Ahmadilivani, Mohammad Hasan, et al.
Published: (2024)

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

HALOC-AxA: An Area/-Energy-Efficient Approximate Adder for Image Processing Application
by: Ziad, Hasnain A., et al.
Published: (2025)

AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs
by: Mrazek, Vojtech, et al.
Published: (2025)

DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration
by: Ghosh, Arkapravo, et al.
Published: (2025)

ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits
by: Sekanina, Lukas, et al.
Published: (2026)

A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

Optimization of Armv9 architecture general large language model inference performance based on Llama.cpp
by: Chen, Longhao, et al.
Published: (2024)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

An ECC-based Fault Tolerance Approach for DNNs
by: Raji, Mohsen, et al.
Published: (2025)

AxMoE: Characterizing the Impact of Approximate Multipliers on Mixture-of-Experts DNN Architectures
by: Shende, Omkar B, et al.
Published: (2026)

ABI: A tightly integrated, unified, sparsity-aware, reconfigurable, compute near-register file/cache GPU architecture with light-weight softmax for deep learning, linear algebra, and Ising compute
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators
by: Taheri, Mahdi, et al.
Published: (2024)

Design high-confidence computers using trusted instructional set architecture and emulators
by: Wang, Shuangbao Paul
Published: (2025)

Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)

Leveraging Recurrent Patterns in Graph Accelerators
by: Rahimi, Masoud, et al.
Published: (2025)

A modular architecture for IMU-based data gloves
by: Carfì, Alessandro, et al.
Published: (2024)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)

GRAMC: General-purpose and reconfigurable analog matrix computing architecture
by: Pan, Lunshuai, et al.
Published: (2025)

Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning
by: Mishty, Kaniz, et al.
Published: (2024)

Pack my weights and run! Minimizing overheads for in-memory computing accelerators
by: Houshmand, Pouya, et al.
Published: (2024)

Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays
by: Suzuki, Yasunari, et al.
Published: (2024)

Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)
by: Oztas, Ali Emre, et al.
Published: (2024)

AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming
by: Sahoo, Siva Satyendra, et al.
Published: (2023)

Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA
by: Carpentieri, Nicolò, et al.
Published: (2024)

HARP: A Taxonomy for Heterogeneous and Hierarchical Processors for Mixed-reuse Workloads
by: Garg, Raveesh, et al.
Published: (2025)

AxOSyn: An Open-source Framework for Synthesizing Novel Approximate Arithmetic Operators
by: Sahoo, Siva Satyendra, et al.
Published: (2025)

The Bicameral Cache: a split cache for vector architectures
by: Rebolledo, Susana, et al.
Published: (2024)

IC-D2S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver Method
by: Abdollahi, Armin, et al.
Published: (2025)

MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
by: Abdollahi, Armin, et al.
Published: (2024)

How to keep pushing ML accelerator performance? Know your rooflines!
by: Verhelst, Marian, et al.
Published: (2025)

Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
by: Colleman, Steven, et al.
Published: (2024)

HALO: Hardware-aware quantization with low critical-path-delay weights for LLM acceleration
by: Juneja, Rohan, et al.
Published: (2025)

On the Impact of ISA Extension on Energy Consumption of I-Cache in Extensible Processors
by: Behboudi, Noushin, et al.
Published: (2024)

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
by: Abdollahi, Armin, et al.
Published: (2026)

Sustainable operation of research infrastructure for novel computing
by: Stradmann, Yannik, et al.
Published: (2025)

CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration
by: Ahn, Bas, et al.
Published: (2026)

EA4RCA:Efficient AIE accelerator design framework for Regular Communication-Avoiding Algorithm
by: Zhang, W. B., et al.
Published: (2024)