AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging
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arXiv
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| Autores principales: | , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
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| _version_ | 1866915519759646720 |
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| author | Lyu, Hongqin Wang, Yonghao Du, Yunlin Shi, Mingyu Chao, Zhiteng Li, Wenxing Wang, Tiancheng Li, Huawei |
| author_facet | Lyu, Hongqin Wang, Yonghao Du, Yunlin Shi, Mingyu Chao, Zhiteng Li, Wenxing Wang, Tiancheng Li, Huawei |
| contents | Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model (LLM) aided assertion generation approaches have recently achieved remarkable progress, existing methods are still unable to effectively identify the relationship between design specifications and RTL designs, which leads to the insufficiency of the generated assertions. To address this issue, we propose AssertGen, an assertion generation framework that automatically generates SystemVerilog assertions (SVA). AssertGen first extracts verification objectives from specifications using a chain-of-thought (CoT) reasoning strategy, then bridges corresponding signals between these objectives and the RTL code to construct a cross-layer signal chain, and finally generates SVAs based on the LLM. Experimental results demonstrate that AssertGen outperforms the existing state-of-the-art methods across several key metrics, such as pass rate of formal property verification (FPV), cone of influence (COI), proof core and mutation testing coverage. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_23674 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging Lyu, Hongqin Wang, Yonghao Du, Yunlin Shi, Mingyu Chao, Zhiteng Li, Wenxing Wang, Tiancheng Li, Huawei Hardware Architecture Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model (LLM) aided assertion generation approaches have recently achieved remarkable progress, existing methods are still unable to effectively identify the relationship between design specifications and RTL designs, which leads to the insufficiency of the generated assertions. To address this issue, we propose AssertGen, an assertion generation framework that automatically generates SystemVerilog assertions (SVA). AssertGen first extracts verification objectives from specifications using a chain-of-thought (CoT) reasoning strategy, then bridges corresponding signals between these objectives and the RTL code to construct a cross-layer signal chain, and finally generates SVAs based on the LLM. Experimental results demonstrate that AssertGen outperforms the existing state-of-the-art methods across several key metrics, such as pass rate of formal property verification (FPV), cone of influence (COI), proof core and mutation testing coverage. |
| title | AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2509.23674 |