AssertFix: Empowering Automated Assertion Fix via Large Language Models
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arXiv
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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866918150013976576 |
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| author | Lyu, Hongqin Du, Yunlin Wang, Yonghao Chao, Zhiteng Wang, Tiancheng Li, Huawei |
| author_facet | Lyu, Hongqin Du, Yunlin Wang, Yonghao Chao, Zhiteng Wang, Tiancheng Li, Huawei |
| contents | Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) effectively specify design properties, but writing and maintaining them manually is challenging and error-prone. Although recent progress of assertion generation methods leveraging large language models (LLMs) have shown great potential in improving assertion quality, they typically treat assertion generation as a final step, leaving the burden of fixing of the incorrect assertions to human effects, which may significantly limits the application of these methods. To address the above limitation, we propose an automatic assertion fix framework based on LLMs, named AssertFix. AsserFix accurately locates the RTL code related to the incorrect assertion, systematically identifies the root causes of the assertion errors, classifies the error type and finally applies dedicated fix strategies to automatically correct these errors, improving the overall quality of the generated assertions. Experimental results show that AssertFix achieves noticeable improvements in both fix rate and verification coverage across the Opencore benchmarks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_23972 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AssertFix: Empowering Automated Assertion Fix via Large Language Models Lyu, Hongqin Du, Yunlin Wang, Yonghao Chao, Zhiteng Wang, Tiancheng Li, Huawei Hardware Architecture Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) effectively specify design properties, but writing and maintaining them manually is challenging and error-prone. Although recent progress of assertion generation methods leveraging large language models (LLMs) have shown great potential in improving assertion quality, they typically treat assertion generation as a final step, leaving the burden of fixing of the incorrect assertions to human effects, which may significantly limits the application of these methods. To address the above limitation, we propose an automatic assertion fix framework based on LLMs, named AssertFix. AsserFix accurately locates the RTL code related to the incorrect assertion, systematically identifies the root causes of the assertion errors, classifies the error type and finally applies dedicated fix strategies to automatically correct these errors, improving the overall quality of the generated assertions. Experimental results show that AssertFix achieves noticeable improvements in both fix rate and verification coverage across the Opencore benchmarks. |
| title | AssertFix: Empowering Automated Assertion Fix via Large Language Models |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2509.23972 |