Cover Image

Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Li, Weihang, Crowley, Pete, Tschand, Arya, Wang, Yu, Pajic, Miroslav, Sorin, Daniel
Format:	Preprint
Published:	2025
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
by: Hassan, Muhammad, et al.
Published: (2025)

ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
by: Narkthong, Nuntipat, et al.
Published: (2025)

Supporting Secured Integration of Microarchitectural Defenses
by: Ramkrishnan, Kartik, et al.
Published: (2026)

FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption
by: Daksha, Lohit, et al.
Published: (2026)

Pre-cache: A Microarchitectural Solution to prevent Meltdown and Spectre
by: Sethumurugan, Subhash, et al.
Published: (2025)

GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption
by: Shivdikar, Kaustubh, et al.
Published: (2023)

Oreo: Protecting ASLR Against Microarchitectural Attacks (Extended Version)
by: Song, Shixin, et al.
Published: (2024)

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands
by: Nam, Hwayong, et al.
Published: (2024)

ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
by: Kvalsvik, Amund Bergland, et al.
Published: (2025)

Exploiting Inaccurate Branch History in Side-Channel Attacks
by: Zhu, Yuhui, et al.
Published: (2025)

Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
by: Bostancı, F. Nisa, et al.
Published: (2025)

PoSyn: Secure Power Side-Channel Aware Synthesis
by: Srivastava, Amisha, et al.
Published: (2025)

Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide
by: Farnaghinejad, Behnam, et al.
Published: (2025)

SemPat: Using Hyperproperty-based Semantic Analysis to Generate Microarchitectural Attack Patterns
by: Godbole, Adwait, et al.
Published: (2024)

PhantomFetch: Obfuscating Loads against Prefetcher Side-Channel Attacks
by: Zhang, Xingzhi, et al.
Published: (2025)

The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs
by: Galli, Davide, et al.
Published: (2024)

FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
by: Jiang, Zhe, et al.
Published: (2025)

RollingCache: Using Runtime Behavior to Defend Against Cache Side Channel Attacks
by: Ojha, Divya, et al.
Published: (2024)

Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory
by: Bostanci, F. Nisa, et al.
Published: (2024)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)

THOR: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
by: Dizani, Farshad, et al.
Published: (2025)

Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
by: Bolat, Alperen, et al.
Published: (2025)

Case Study: Horizontal Side-Channel Analysis Attack against Elliptic Curve Scalar Multiplication Accelerator under Laser Illumination
by: Petryk, Dmytro, et al.
Published: (2026)

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography
by: Tan, Weihang, et al.
Published: (2021)

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption
by: Tan, Weihang, et al.
Published: (2023)

CipherGuard: Compiler-aided Mitigation against Ciphertext Side-channel Attacks
by: Jiang, Ke, et al.
Published: (2025)

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024)

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
by: Pinto, Sandro, et al.
Published: (2024)

System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
by: Cunha, Luis, et al.
Published: (2026)

Side-channel Inference of User Activities in AR/VR Using GPU Profiling
by: Son, Seonghun, et al.
Published: (2025)

Memory DisOrder: Memory Re-orderings as a Timerless Side-channel
by: Siddens, Sean, et al.
Published: (2026)

PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference
by: Narkthong, Nuntipat, et al.
Published: (2025)

Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators
by: Weerasena, Hansika, et al.
Published: (2023)

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
by: Wistoff, Nils, et al.
Published: (2022)

RogueRFM: Attacking Refresh Management for Covert-Channel and Denial-of-Service
by: Taneja, Hritvik, et al.
Published: (2025)

The Impact of Logic Locking on Confidentiality: An Automated Evaluation
by: Reimann, Lennart M., et al.
Published: (2025)

Systematic Evaluation of Randomized Cache Designs against Cache Occupancy
by: Chakraborty, Anirban, et al.
Published: (2023)

Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025)

eFPE: Design, Implementation, and Evaluation of a Lightweight Format-Preserving Encryption Algorithm for Embedded Systems
by: Hegde, Nishant Vasantkumar, et al.
Published: (2025)

LaMoS: Enabling Efficient Large Number Modular Multiplication through SRAM-based CiM Acceleration
by: Li, Haomin, et al.
Published: (2025)