In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866916987022606336 |
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| author | Li, Jindan Wu, Zhaoxian Liu, Gaowen Gokmen, Tayfun Chen, Tianyi |
| author_facet | Li, Jindan Wu, Zhaoxian Liu, Gaowen Gokmen, Tayfun Chen, Tianyi |
| contents | Analog in-memory computing (AIMC) accelerators enable efficient deep neural network computation directly within memory using resistive crossbar arrays, where model parameters are represented by the conductance states of memristive devices. However, effective in-memory training typically requires at least 8-bit conductance states to match digital baselines. Realizing such fine-grained states is costly and often requires complex noise mitigation techniques that increase circuit complexity and energy consumption. In practice, many promising memristive devices such as ReRAM offer only about 4-bit resolution due to fabrication constraints, and this limited update precision substantially degrades training accuracy. To enable on-chip training with these limited-state devices, this paper proposes a \emph{residual learning} framework that sequentially learns on multiple crossbar tiles to compensate the residual errors from low-precision weight updates. Our theoretical analysis shows that the optimality gap shrinks with the number of tiles and achieves a linear convergence rate. Experiments on standard image classification benchmarks demonstrate that our method consistently outperforms state-of-the-art in-memory analog training strategies under limited-state settings, while incurring only moderate hardware overhead as confirmed by our cost analysis. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_02516 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning Li, Jindan Wu, Zhaoxian Liu, Gaowen Gokmen, Tayfun Chen, Tianyi Machine Learning Hardware Architecture Optimization and Control Analog in-memory computing (AIMC) accelerators enable efficient deep neural network computation directly within memory using resistive crossbar arrays, where model parameters are represented by the conductance states of memristive devices. However, effective in-memory training typically requires at least 8-bit conductance states to match digital baselines. Realizing such fine-grained states is costly and often requires complex noise mitigation techniques that increase circuit complexity and energy consumption. In practice, many promising memristive devices such as ReRAM offer only about 4-bit resolution due to fabrication constraints, and this limited update precision substantially degrades training accuracy. To enable on-chip training with these limited-state devices, this paper proposes a \emph{residual learning} framework that sequentially learns on multiple crossbar tiles to compensate the residual errors from low-precision weight updates. Our theoretical analysis shows that the optimality gap shrinks with the number of tiles and achieves a linear convergence rate. Experiments on standard image classification benchmarks demonstrate that our method consistently outperforms state-of-the-art in-memory analog training strategies under limited-state settings, while incurring only moderate hardware overhead as confirmed by our cost analysis. |
| title | In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning |
| topic | Machine Learning Hardware Architecture Optimization and Control |
| url | https://arxiv.org/abs/2510.02516 |