Saved in:
| Main Authors: | Ibnat, Zahin, Calzada, Paul E., Ihtemam, Rasin Mohammed, Saha, Sujan Kumar, Zhou, Jingbo, Farahmandi, Farimah, Tehranipoor, Mark |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2510.05327 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
by: Calzada, Paul E., et al.
Published: (2025)
by: Calzada, Paul E., et al.
Published: (2025)
SVAgent: AI Agent for Hardware Security Verification Assertion
by: Guo, Rui, et al.
Published: (2025)
by: Guo, Rui, et al.
Published: (2025)
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)
by: Roy, Prithwish Basu, et al.
Published: (2025)
EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
by: Guo, Ping, et al.
Published: (2025)
by: Guo, Ping, et al.
Published: (2025)
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)
by: Niu, Juxin, et al.
Published: (2025)
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
by: Qin, Haiyan, et al.
Published: (2025)
by: Qin, Haiyan, et al.
Published: (2025)
Exploring the Agentic Frontier of Verilog Code Generation
by: Yubeaton, Patrick, et al.
Published: (2026)
by: Yubeaton, Patrick, et al.
Published: (2026)
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
by: Tan, Yan, et al.
Published: (2026)
by: Tan, Yan, et al.
Published: (2026)
TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
by: Abdollahi, Armin, et al.
Published: (2026)
by: Abdollahi, Armin, et al.
Published: (2026)
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
by: Tan, Yan, et al.
Published: (2025)
by: Tan, Yan, et al.
Published: (2025)
HDLFORGE: A Two-Stage Multi-Agent Framework for Efficient Verilog Code Generation with Adaptive Model Escalation
by: Abdollahi, Armin, et al.
Published: (2026)
by: Abdollahi, Armin, et al.
Published: (2026)
QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
by: Zhu, Yaoyu, et al.
Published: (2025)
by: Zhu, Yaoyu, et al.
Published: (2025)
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
by: Collini, Luca, et al.
Published: (2026)
by: Collini, Luca, et al.
Published: (2026)
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
by: Abdelatty, Manar, et al.
Published: (2024)
by: Abdelatty, Manar, et al.
Published: (2024)
Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
by: Yang, Guang, et al.
Published: (2025)
by: Yang, Guang, et al.
Published: (2025)
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
by: Wang, Ning, et al.
Published: (2024)
by: Wang, Ning, et al.
Published: (2024)
Speculative Decoding for Verilog: Speed and Quality, All in One
by: Xu, Changran, et al.
Published: (2025)
by: Xu, Changran, et al.
Published: (2025)
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
by: Yang, Yiyao, et al.
Published: (2025)
by: Yang, Yiyao, et al.
Published: (2025)
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
by: Gao, Mingzhe, et al.
Published: (2024)
by: Gao, Mingzhe, et al.
Published: (2024)
Python-based DSL for generating Verilog model of Synchronous Digital Circuits
by: Datar, Mandar, et al.
Published: (2024)
by: Datar, Mandar, et al.
Published: (2024)
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
by: Zhao, Zhuorui, et al.
Published: (2025)
by: Zhao, Zhuorui, et al.
Published: (2025)
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
by: Pinckney, Nathaniel, et al.
Published: (2024)
by: Pinckney, Nathaniel, et al.
Published: (2024)
SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
by: Hu, Ziteng, et al.
Published: (2025)
by: Hu, Ziteng, et al.
Published: (2025)
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
by: Fang, Zhigang, et al.
Published: (2025)
by: Fang, Zhigang, et al.
Published: (2025)
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)
by: Fang, Wenji, et al.
Published: (2024)
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
by: Zhang, Yang, et al.
Published: (2025)
by: Zhang, Yang, et al.
Published: (2025)
The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
by: Yang, Guang, et al.
Published: (2025)
by: Yang, Guang, et al.
Published: (2025)
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
by: Thorat, Kiran, et al.
Published: (2025)
by: Thorat, Kiran, et al.
Published: (2025)
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
by: Liu, Mingjie, et al.
Published: (2024)
by: Liu, Mingjie, et al.
Published: (2024)
VFlow: Discovering Optimal Agentic Workflows for Verilog Generation
by: Wei, Yangbo, et al.
Published: (2025)
by: Wei, Yangbo, et al.
Published: (2025)
MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation
by: Zhang, Yongan, et al.
Published: (2024)
by: Zhang, Yongan, et al.
Published: (2024)
DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model
by: Liu, Yi, et al.
Published: (2025)
by: Liu, Yi, et al.
Published: (2025)
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
by: Zhao, Jiayu, et al.
Published: (2025)
by: Zhao, Jiayu, et al.
Published: (2025)
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
by: Jin, Pengwei, et al.
Published: (2025)
by: Jin, Pengwei, et al.
Published: (2025)
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
by: Chang, Kaiyan, et al.
Published: (2024)
by: Chang, Kaiyan, et al.
Published: (2024)
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
by: Yao, Bingkun, et al.
Published: (2024)
by: Yao, Bingkun, et al.
Published: (2024)
VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)
by: Qi, Haomin, et al.
Published: (2025)
Similar Items
-
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
by: Calzada, Paul E., et al.
Published: (2025) -
SVAgent: AI Agent for Hardware Security Verification Assertion
by: Guo, Rui, et al.
Published: (2025) -
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025) -
EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
by: Guo, Ping, et al.
Published: (2025) -
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)