How long can you sleep? Idle Time System Inefficiencies and Opportunities
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866912637903699968 |
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| author | Antoniou, Georgia Volos, Haris Yahya, Jawad Haj Sazeides, Yiannakis |
| author_facet | Antoniou, Georgia Volos, Haris Yahya, Jawad Haj Sazeides, Yiannakis |
| contents | This work introduces a model-based framework that reveals the idle opportunity of modern servers running latency-critical applications. Specifically, three queuing models, M/M/1, cxM/M/1, and M/M/c, are used to estimate the theoretical idle time distribution at the CPU core and system (package) level. A comparison of the actual idleness of a real server and that from the theoretical models reveals significant missed opportunities to enter deep idle states. This inefficiency is attributed to the idle-governor inaccuracy and the high latency to transition to/from legacy deep-idle states. The proposed methodology offers the means for an early-stage design exploration and insights into idle time behavior and opportunities for varying server system configurations and load. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_07449 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | How long can you sleep? Idle Time System Inefficiencies and Opportunities Antoniou, Georgia Volos, Haris Yahya, Jawad Haj Sazeides, Yiannakis Hardware Architecture C.1.0 This work introduces a model-based framework that reveals the idle opportunity of modern servers running latency-critical applications. Specifically, three queuing models, M/M/1, cxM/M/1, and M/M/c, are used to estimate the theoretical idle time distribution at the CPU core and system (package) level. A comparison of the actual idleness of a real server and that from the theoretical models reveals significant missed opportunities to enter deep idle states. This inefficiency is attributed to the idle-governor inaccuracy and the high latency to transition to/from legacy deep-idle states. The proposed methodology offers the means for an early-stage design exploration and insights into idle time behavior and opportunities for varying server system configurations and load. |
| title | How long can you sleep? Idle Time System Inefficiencies and Opportunities |
| topic | Hardware Architecture C.1.0 |
| url | https://arxiv.org/abs/2510.07449 |