An Energy-Efficient Edge Coprocessor for Neural Rendering with Explicit Data Reuse Strategies
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arXiv
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| Auteurs principaux: | , , , , , , , , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866914082330771456 |
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| author | Yuan, Binzhe Zhang, Xiangyu Zheng, Zeyu Zhang, Yuefeng Wan, Haochuan Yuan, Zhechen Chen, Junsheng He, Yunxiang Ding, Junran Zhang, Xiaoming Rao, Chaolin Su, Wenyan Zhou, Pingqiang Yu, Jingyi Lou, Xin |
| author_facet | Yuan, Binzhe Zhang, Xiangyu Zheng, Zeyu Zhang, Yuefeng Wan, Haochuan Yuan, Zhechen Chen, Junsheng He, Yunxiang Ding, Junran Zhang, Xiaoming Rao, Chaolin Su, Wenyan Zhou, Pingqiang Yu, Jingyi Lou, Xin |
| contents | Neural radiance fields (NeRF) have transformed 3D reconstruction and rendering, facilitating photorealistic image synthesis from sparse viewpoints. This work introduces an explicit data reuse neural rendering (EDR-NR) architecture, which reduces frequent external memory accesses (EMAs) and cache misses by exploiting the spatial locality from three phases, including rays, ray packets (RPs), and samples. The EDR-NR architecture features a four-stage scheduler that clusters rays on the basis of Z-order, prioritize lagging rays when ray divergence happens, reorders RPs based on spatial proximity, and issues samples out-of-orderly (OoO) according to the availability of on-chip feature data. In addition, a four-tier hierarchical RP marching (HRM) technique is integrated with an axis-aligned bounding box (AABB) to facilitate spatial skipping (SS), reducing redundant computations and improving throughput. Moreover, a balanced allocation strategy for feature storage is proposed to mitigate SRAM bank conflicts. Fabricated using a 40 nm process with a die area of 10.5 mmX, the EDR-NR chip demonstrates a 2.41X enhancement in normalized energy efficiency, a 1.21X improvement in normalized area efficiency, a 1.20X increase in normalized throughput, and a 53.42% reduction in on-chip SRAM consumption compared to state-of-the-art accelerators. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_07667 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | An Energy-Efficient Edge Coprocessor for Neural Rendering with Explicit Data Reuse Strategies Yuan, Binzhe Zhang, Xiangyu Zheng, Zeyu Zhang, Yuefeng Wan, Haochuan Yuan, Zhechen Chen, Junsheng He, Yunxiang Ding, Junran Zhang, Xiaoming Rao, Chaolin Su, Wenyan Zhou, Pingqiang Yu, Jingyi Lou, Xin Image and Video Processing Neural radiance fields (NeRF) have transformed 3D reconstruction and rendering, facilitating photorealistic image synthesis from sparse viewpoints. This work introduces an explicit data reuse neural rendering (EDR-NR) architecture, which reduces frequent external memory accesses (EMAs) and cache misses by exploiting the spatial locality from three phases, including rays, ray packets (RPs), and samples. The EDR-NR architecture features a four-stage scheduler that clusters rays on the basis of Z-order, prioritize lagging rays when ray divergence happens, reorders RPs based on spatial proximity, and issues samples out-of-orderly (OoO) according to the availability of on-chip feature data. In addition, a four-tier hierarchical RP marching (HRM) technique is integrated with an axis-aligned bounding box (AABB) to facilitate spatial skipping (SS), reducing redundant computations and improving throughput. Moreover, a balanced allocation strategy for feature storage is proposed to mitigate SRAM bank conflicts. Fabricated using a 40 nm process with a die area of 10.5 mmX, the EDR-NR chip demonstrates a 2.41X enhancement in normalized energy efficiency, a 1.21X improvement in normalized area efficiency, a 1.20X increase in normalized throughput, and a 53.42% reduction in on-chip SRAM consumption compared to state-of-the-art accelerators. |
| title | An Energy-Efficient Edge Coprocessor for Neural Rendering with Explicit Data Reuse Strategies |
| topic | Image and Video Processing |
| url | https://arxiv.org/abs/2510.07667 |