ACT: Automatically Generating Compiler Backends from Tensor Accelerator ISA Descriptions
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arXiv
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| Main Authors: | Jain, Devansh, Pardeshi, Akash, Frigo, Marco, Patel, Krut, Khulbe, Kaustubh, Arora, Jai, Mendis, Charith |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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