Efficient In-Memory Acceleration of Sparse Block Diagonal LLMs
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866908589308772352 |
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| author | de Lima, João Paulo Cardoso Dietrich, Marc Castrillon, Jeronimo Khan, Asif Ali |
| author_facet | de Lima, João Paulo Cardoso Dietrich, Marc Castrillon, Jeronimo Khan, Asif Ali |
| contents | Structured sparsity enables deploying large language models (LLMs) on resource-constrained systems. Approaches like dense-to-sparse fine-tuning are particularly compelling, achieving remarkable structured sparsity by reducing the model size by over 6.7x, while still maintaining acceptable accuracy. Despite this reduction, LLM inference, especially the decode stage being inherently memory-bound, is extremely expensive on conventional Von-Neumann architectures. Compute-in-memory (CIM) architectures mitigate this by performing computations directly in memory, and when paired with sparse LLMs, enable storing and computing the entire model in memory, eliminating the data movement on the off-chip bus and improving efficiency. Nonetheless, naively mapping sparse matrices onto CIM arrays leads to poor array utilization and diminished computational efficiency. In this paper, we present an automated framework with novel mapping and scheduling strategies to accelerate sparse LLM inference on CIM accelerators. By exploiting block-diagonal sparsity, our approach improves CIM array utilization by over 50%, achieving more than 4x reduction in both memory footprint and the number of required floating-point operations. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_11192 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Efficient In-Memory Acceleration of Sparse Block Diagonal LLMs de Lima, João Paulo Cardoso Dietrich, Marc Castrillon, Jeronimo Khan, Asif Ali Hardware Architecture Machine Learning Structured sparsity enables deploying large language models (LLMs) on resource-constrained systems. Approaches like dense-to-sparse fine-tuning are particularly compelling, achieving remarkable structured sparsity by reducing the model size by over 6.7x, while still maintaining acceptable accuracy. Despite this reduction, LLM inference, especially the decode stage being inherently memory-bound, is extremely expensive on conventional Von-Neumann architectures. Compute-in-memory (CIM) architectures mitigate this by performing computations directly in memory, and when paired with sparse LLMs, enable storing and computing the entire model in memory, eliminating the data movement on the off-chip bus and improving efficiency. Nonetheless, naively mapping sparse matrices onto CIM arrays leads to poor array utilization and diminished computational efficiency. In this paper, we present an automated framework with novel mapping and scheduling strategies to accelerate sparse LLM inference on CIM accelerators. By exploiting block-diagonal sparsity, our approach improves CIM array utilization by over 50%, achieving more than 4x reduction in both memory footprint and the number of required floating-point operations. |
| title | Efficient In-Memory Acceleration of Sparse Block Diagonal LLMs |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2510.11192 |