A protocol to reduce worst-case latency in deflection-based on-chip networks
Fuente:
arXiv
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| Auteur principal: | |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866908589422018560 |
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| author | Indrusiak, Leandro Soares |
| author_facet | Indrusiak, Leandro Soares |
| contents | We present a novel protocol that reduces worst-case packet latency in deflection-based on-chip interconnect networks. It enforces the deflection of the header of a packet but not its payload, resulting in a reduction in overall network traffic and, more importantly, worst-case packet latency due to decreased pre-injection latency. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_11361 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A protocol to reduce worst-case latency in deflection-based on-chip networks Indrusiak, Leandro Soares Networking and Internet Architecture Performance We present a novel protocol that reduces worst-case packet latency in deflection-based on-chip interconnect networks. It enforces the deflection of the header of a packet but not its payload, resulting in a reduction in overall network traffic and, more importantly, worst-case packet latency due to decreased pre-injection latency. |
| title | A protocol to reduce worst-case latency in deflection-based on-chip networks |
| topic | Networking and Internet Architecture Performance |
| url | https://arxiv.org/abs/2510.11361 |