Cover Image

Multimodal Chip Physical Design Engineer Assistant

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Tsai, Yun-Da, Chao, Chang-Yu, Shen, Liang-Yeh, Lin, Tsung-Han, Yang, Haoyu, Ho, Mark, Lu, Yi-Chen, Liu, Wen-Hao, Lin, Shou-De, Ren, Haoxing
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence Machine Learning
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
by: Tsai, Yun-Da, et al.
Published: (2023)

Intelligent OPC Engineer Assistant for Semiconductor Manufacturing
by: Chen, Guojin, et al.
Published: (2024)

ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
by: Deng, Chenhui, et al.
Published: (2024)

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
by: Liu, Mingjie, et al.
Published: (2024)

Large Language Model (LLM) for Standard Cell Layout Design Optimization
by: Ho, Chia-Tung, et al.
Published: (2024)

Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
by: Pinckney, Nathaniel, et al.
Published: (2025)

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)

FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
by: Bai, Yunsheng, et al.
Published: (2025)

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
by: Ho, Chia-Tung, et al.
Published: (2025)

Learning Library Cell Representations in Vector Space
by: Liang, Rongjian, et al.
Published: (2025)

Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
by: Zhu, Jingchen, et al.
Published: (2024)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
by: Fang, Wenji, et al.
Published: (2025)

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
by: Yu, Zhongzhi, et al.
Published: (2025)

Search-in-Memory (SiM): Reliable, Versatile, and Efficient Data Matching in SSD's NAND Flash Memory Chip for Data Indexing Acceleration
by: Chen, Yun-Chih, et al.
Published: (2024)

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
by: Yu, Cunxi, et al.
Published: (2026)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference
by: Nair, Harideep, et al.
Published: (2024)

HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
by: Tsai, Pei-Huan, et al.
Published: (2026)

DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
by: Chang, Chen-Chia, et al.
Published: (2024)

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
by: Meng, Chang-Chih, et al.
Published: (2026)

SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
by: Xuan, Wei, et al.
Published: (2025)

Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
by: Chen, Guan-Cheng, et al.
Published: (2025)

MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
by: Raj, Ritik, et al.
Published: (2025)

Towards Efficient and Accurate Detection of On-Chip Fail-Slow Failures for Many-Core Accelerators
by: Wu, Junchi, et al.
Published: (2025)

GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
by: Lu, Tsung-Han, et al.
Published: (2026)

ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
by: Yu, Zhongkai, et al.
Published: (2026)

Large Processor Chip Model
by: Chang, Kaiyan, et al.
Published: (2025)

Subitizing-Inspired_Large_Language_Models_for_Floorplanning
by: Lu, Shao-Chien, et al.
Published: (2025)

3D MPSoC with On-Chip Cache Support -- Design and Exploitation
by: Cataldo, Rodrigo, et al.
Published: (2025)

Improving Chip Design Enablement for Universities in Europe -- A Position Paper
by: Krupp, Lukas, et al.
Published: (2025)

Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques
by: Lin, Qun-Kai, et al.
Published: (2025)

gem5 Co-Pilot: AI Assistant Agent for Architectural Design Space Exploration
by: Fu, Zuoming, et al.
Published: (2025)

A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
by: Zhou, Wenyong, et al.
Published: (2025)

QiMeng: Fully Automated Hardware and Software Design for Processor Chip
by: Zhang, Rui, et al.
Published: (2025)

PIM-FW: Hardware-Software Co-Design of All-pairs Shortest Paths in DRAM
by: Lu, Tsung-Han, et al.
Published: (2025)

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)

ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
by: Bai, Kangbo, et al.
Published: (2026)

SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)

ReCross: Efficient Embedding Reduction Scheme for In-Memory Computing using ReRAM-Based Crossbar
by: Lai, Yu-Hong, et al.
Published: (2025)

FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design
by: Nazzal, Mahmoud, et al.
Published: (2025)

Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
by: Pinckney, Nathaniel, et al.
Published: (2024)