basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
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arXiv
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| Auteurs principaux: | , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866909853961682944 |
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| author | Kang, Hyun Woo Choi, Ji Woong |
| author_facet | Kang, Hyun Woo Choi, Ji Woong |
| contents | This paper introduces BASIC_RV32s, an open-source framework providing a practical microarchitectural roadmap for the RISC-V RV32I architecture, addressing the gap between theoretical knowledge and hardware implementation. Following the classic Patterson and Hennessy methodology, the design evolves from a basic single-cycle core to a 5-stage pipelined core design with full hazard forwarding, dynamic branch prediction, and exception handling. For verification, the final core design is integrated into a System-on-Chip (SoC) with Universal Asynchronous Receiver-Transmitter (UART) communication implemented on a Xilinx Artix-7 Field-Programmable Gate Array (FPGA), achieving 1.09 Dhrystone million instructions per second per megahertz (DMIPS/MHz) at 50 MHz. By releasing all Register-Transfer Level (RTL) source code, signal-level logic block diagrams, and development logs under MIT license on GitHub, BASIC_RV32s offers a reproducible instructional pathway for the open-source hardware ecosystem. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_15887 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I Kang, Hyun Woo Choi, Ji Woong Hardware Architecture C.1.0; B.7.1 This paper introduces BASIC_RV32s, an open-source framework providing a practical microarchitectural roadmap for the RISC-V RV32I architecture, addressing the gap between theoretical knowledge and hardware implementation. Following the classic Patterson and Hennessy methodology, the design evolves from a basic single-cycle core to a 5-stage pipelined core design with full hazard forwarding, dynamic branch prediction, and exception handling. For verification, the final core design is integrated into a System-on-Chip (SoC) with Universal Asynchronous Receiver-Transmitter (UART) communication implemented on a Xilinx Artix-7 Field-Programmable Gate Array (FPGA), achieving 1.09 Dhrystone million instructions per second per megahertz (DMIPS/MHz) at 50 MHz. By releasing all Register-Transfer Level (RTL) source code, signal-level logic block diagrams, and development logs under MIT license on GitHub, BASIC_RV32s offers a reproducible instructional pathway for the open-source hardware ecosystem. |
| title | basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I |
| topic | Hardware Architecture C.1.0; B.7.1 |
| url | https://arxiv.org/abs/2510.15887 |