LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
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arXiv
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| Autori principali: | , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866911218205196288 |
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| author | Thorat, Kiran Zhao, Jiahui Liu, Yaotian Hasan, Amit Peng, Hongwu Xie, Xi Lei, Bin Ding, Caiwen |
| author_facet | Thorat, Kiran Zhao, Jiahui Liu, Yaotian Hasan, Amit Peng, Hongwu Xie, Xi Lei, Bin Ding, Caiwen |
| contents | Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the field of chip design using LLMs, specifically in Power- Performance-Area (PPA) optimization and the generation of accurate Verilog codes for circuit designs. We introduce a novel framework VeriPPA designed to optimize PPA and generate Verilog code using LLMs. Our method includes a two-stage process where the first stage focuses on improving the functional and syntactic correctness of the generated Verilog codes, while the second stage focuses on optimizing the Verilog codes to meet PPA constraints of circuit designs, a crucial element of chip design. Our framework achieves an 81.37% success rate in syntactic correctness and 62.06% in functional correctness for code genera- tion, outperforming current state-of-the-art (SOTA) methods. On the RTLLM dataset. On the VerilogEval dataset, our framework achieves 99.56% syntactic correctness and 43.79% functional correctness, also surpassing SOTA, which stands at 92.11% for syntactic correctness and 33.57% for functional correctness. Furthermore, Our framework able to optimize the PPA of the designs. These results highlight the potential of LLMs in handling complex technical areas and indicate an encouraging development in the automation of chip design processes. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_15899 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models Thorat, Kiran Zhao, Jiahui Liu, Yaotian Hasan, Amit Peng, Hongwu Xie, Xi Lei, Bin Ding, Caiwen Hardware Architecture Machine Learning Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the field of chip design using LLMs, specifically in Power- Performance-Area (PPA) optimization and the generation of accurate Verilog codes for circuit designs. We introduce a novel framework VeriPPA designed to optimize PPA and generate Verilog code using LLMs. Our method includes a two-stage process where the first stage focuses on improving the functional and syntactic correctness of the generated Verilog codes, while the second stage focuses on optimizing the Verilog codes to meet PPA constraints of circuit designs, a crucial element of chip design. Our framework achieves an 81.37% success rate in syntactic correctness and 62.06% in functional correctness for code genera- tion, outperforming current state-of-the-art (SOTA) methods. On the RTLLM dataset. On the VerilogEval dataset, our framework achieves 99.56% syntactic correctness and 43.79% functional correctness, also surpassing SOTA, which stands at 92.11% for syntactic correctness and 33.57% for functional correctness. Furthermore, Our framework able to optimize the PPA of the designs. These results highlight the potential of LLMs in handling complex technical areas and indicate an encouraging development in the automation of chip design processes. |
| title | LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models |
| topic | Hardware Architecture Machine Learning |
| url | https://arxiv.org/abs/2510.15899 |