Saved in:
| Main Authors: | Magalhães, Philippe, Fresse, Virginie, Suffran, Benoît, Alata, Olivier |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2510.15930 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
by: Magalhães, Philippe, et al.
Published: (2025)
by: Magalhães, Philippe, et al.
Published: (2025)
Energy-Aware FPGA Implementation of Spiking Neural Network with LIF Neurons
by: Ali, Asmer Hamid, et al.
Published: (2024)
by: Ali, Asmer Hamid, et al.
Published: (2024)
Efficient Implementation of a Multi-Layer Gradient-Free Online-Trainable Spiking Neural Network on FPGA
by: Mehrabi, Ali, et al.
Published: (2023)
by: Mehrabi, Ali, et al.
Published: (2023)
A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2025)
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2025)
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
by: Sestito, Cristian, et al.
Published: (2024)
by: Sestito, Cristian, et al.
Published: (2024)
Variability-Aware Approximate Circuit Synthesis via Genetic Optimization
by: Balaskas, Konstantinos, et al.
Published: (2023)
by: Balaskas, Konstantinos, et al.
Published: (2023)
Functional Stability of Software-Hardware Neural Network Implementation The NeuroComp Project
by: Oleksii, Bychkov, et al.
Published: (2025)
by: Oleksii, Bychkov, et al.
Published: (2025)
Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge
by: Carpegna, Alessio, et al.
Published: (2024)
by: Carpegna, Alessio, et al.
Published: (2024)
ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors
by: Wu, Haoran, et al.
Published: (2025)
by: Wu, Haoran, et al.
Published: (2025)
Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons
by: Kimura, Nanako, et al.
Published: (2024)
by: Kimura, Nanako, et al.
Published: (2024)
Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers
by: Dong, Pingcheng, et al.
Published: (2024)
by: Dong, Pingcheng, et al.
Published: (2024)
Embedding Hardware Approximations in Discrete Genetic-based Training for Printed MLPs
by: Afentaki, Florentia, et al.
Published: (2024)
by: Afentaki, Florentia, et al.
Published: (2024)
NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2026)
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2026)
Approximate ADCs for In-Memory Computing
by: Ghosh, Arkapravo, et al.
Published: (2024)
by: Ghosh, Arkapravo, et al.
Published: (2024)
A Synthesizable RTL Implementation of Predictive Coding Networks
by: Oh, Timothy
Published: (2026)
by: Oh, Timothy
Published: (2026)
NeuroFlex: Column-Exact ANN-SNN Co-Execution Accelerator with Cost-Guided Scheduling
by: Manjunath, Varun, et al.
Published: (2025)
by: Manjunath, Varun, et al.
Published: (2025)
SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
by: Gunawardana, Kanishka, et al.
Published: (2026)
by: Gunawardana, Kanishka, et al.
Published: (2026)
ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
by: Kumar, Sonu, et al.
Published: (2025)
by: Kumar, Sonu, et al.
Published: (2025)
Darwin3: A large-scale neuromorphic chip with a Novel ISA and On-Chip Learning
by: Ma, De, et al.
Published: (2023)
by: Ma, De, et al.
Published: (2023)
Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing
by: Yousefzadeh, Amirreza, et al.
Published: (2026)
by: Yousefzadeh, Amirreza, et al.
Published: (2026)
SAGA: Synthesis Augmentation with Genetic Algorithms for In-Memory Sequence Optimization
by: Robins, Andey, et al.
Published: (2024)
by: Robins, Andey, et al.
Published: (2024)
Automated Placement of Analog Integrated Circuits using Priority-based Constructive Heuristic
by: Grus, Josef, et al.
Published: (2024)
by: Grus, Josef, et al.
Published: (2024)
An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors
by: Su, Zhe, et al.
Published: (2024)
by: Su, Zhe, et al.
Published: (2024)
Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks
by: Lister, Devon, et al.
Published: (2025)
by: Lister, Devon, et al.
Published: (2025)
FlexNN: A Dataflow-aware Flexible Deep Learning Accelerator for Energy-Efficient Edge Devices
by: Raha, Arnab, et al.
Published: (2024)
by: Raha, Arnab, et al.
Published: (2024)
Wet TinyML: Chemical Neural Network Using Gene Regulation and Cell Plasticity
by: Somathilaka, Samitha, et al.
Published: (2024)
by: Somathilaka, Samitha, et al.
Published: (2024)
YANA: Bridging the Neuromorphic Simulation-to-Hardware Gap
by: Pachideh, Brian, et al.
Published: (2026)
by: Pachideh, Brian, et al.
Published: (2026)
A 0.5-V Linear Neuromorphic Voltage-to-Spike Encoder Using a Bulk-Driven Transconductor
by: Akbari, Meysam, et al.
Published: (2026)
by: Akbari, Meysam, et al.
Published: (2026)
RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN
by: Khan, Mohd Faisal, et al.
Published: (2025)
by: Khan, Mohd Faisal, et al.
Published: (2025)
A Quarter of a Century of Neuromorphic Architectures on FPGAs -- an Overview
by: Szczerek, Wiktor J., et al.
Published: (2025)
by: Szczerek, Wiktor J., et al.
Published: (2025)
Spiking Transformer Hardware Accelerators in 3D Integration
by: Xu, Boxun, et al.
Published: (2024)
by: Xu, Boxun, et al.
Published: (2024)
E2ATST: A Temporal-Spatial Optimized Energy-Efficient Architecture for Training Spiking Transformer
by: Ma, Yunhao, et al.
Published: (2025)
by: Ma, Yunhao, et al.
Published: (2025)
Flexi-NeurA: A Configurable Neuromorphic Accelerator with Adaptive Bit-Precision Exploration for Edge SNNs
by: Farahani, Mohammad, et al.
Published: (2026)
by: Farahani, Mohammad, et al.
Published: (2026)
Core Placement Optimization of Many-core Brain-Inspired Near-Storage Systems for Spiking Neural Network Training
by: Zhu, Xueke, et al.
Published: (2024)
by: Zhu, Xueke, et al.
Published: (2024)
IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
by: Szczerek, Wiktor J., et al.
Published: (2025)
by: Szczerek, Wiktor J., et al.
Published: (2025)
Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons
by: Afentaki, Florentia, et al.
Published: (2024)
by: Afentaki, Florentia, et al.
Published: (2024)
A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware
by: Ronzani, Marco, et al.
Published: (2026)
by: Ronzani, Marco, et al.
Published: (2026)
Hardware-Aware Model Design and Training of Silicon-based Analog Neural Networks
by: Filippeschi, Giulio, et al.
Published: (2025)
by: Filippeschi, Giulio, et al.
Published: (2025)
HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators
by: Vaziri, Mobin, et al.
Published: (2024)
by: Vaziri, Mobin, et al.
Published: (2024)
UniSpike: Accelerating Spiking Neural Networks on Neuromorphic Systems via Eliminating Address Redundancy
by: Xing, Qinghui, et al.
Published: (2026)
by: Xing, Qinghui, et al.
Published: (2026)
Similar Items
-
A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
by: Magalhães, Philippe, et al.
Published: (2025) -
Energy-Aware FPGA Implementation of Spiking Neural Network with LIF Neurons
by: Ali, Asmer Hamid, et al.
Published: (2024) -
Efficient Implementation of a Multi-Layer Gradient-Free Online-Trainable Spiking Neural Network on FPGA
by: Mehrabi, Ali, et al.
Published: (2023) -
A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks
by: Hafiz, Muhammad Ihsan Al, et al.
Published: (2025) -
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
by: Sestito, Cristian, et al.
Published: (2024)