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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2510.16698 |
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| _version_ | 1866915563023892480 |
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| author | Yasmin, Rafichha Jahan, Ishrat Omar, Abdelrahman Baten, Md. Zunaid Rashid, A. B. M. Harun-ur Joy, Soumitra |
| author_facet | Yasmin, Rafichha Jahan, Ishrat Omar, Abdelrahman Baten, Md. Zunaid Rashid, A. B. M. Harun-ur Joy, Soumitra |
| contents | This work introduces an electromagnetic metastructure based interconnect design that could address the critical need for electrical bandwidth and heat dissipation in high-speed, chiplet integration. We leverage silicon as the substrate for its superior thermal properties, and to counteract its high dielectric constant that typically causes high mutual capacitance among interconnects, we've engineered a periodically corrugated, compact metallic structure enabling signal propagation via strongly confined spoof surface plasmon polaritons (SSPPs). By placing this engineered metal on a $50$ $μ$m oxide layer atop Si substrate, we achieved a low insertion loss of $0.015$ dB/cm and a $10$ dB reduction in crosstalk noise within $5$ GHz, resulting in a bandwidth $2.5\times$ as high as that of a standard microstriplines of the same footprint. Furthermore, a $5$ ns input pulse showed minimal distortion and a $0.13$ ns/cm propagation delay in our proposed interconnect. Critically, the thin oxide layer minimally impacted the heat dissipation of Si substrate, demonstrating a fourfold reduction in temperature compared to an FR4 substrate. These full-wave simulation-supported findings present a viable pathway for high-density, thermally efficient interconnects in advanced packaging. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_16698 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Electrical and Thermal Performance Tuning of Spoof Plasmonic Interconnect Yasmin, Rafichha Jahan, Ishrat Omar, Abdelrahman Baten, Md. Zunaid Rashid, A. B. M. Harun-ur Joy, Soumitra Optics Applied Physics This work introduces an electromagnetic metastructure based interconnect design that could address the critical need for electrical bandwidth and heat dissipation in high-speed, chiplet integration. We leverage silicon as the substrate for its superior thermal properties, and to counteract its high dielectric constant that typically causes high mutual capacitance among interconnects, we've engineered a periodically corrugated, compact metallic structure enabling signal propagation via strongly confined spoof surface plasmon polaritons (SSPPs). By placing this engineered metal on a $50$ $μ$m oxide layer atop Si substrate, we achieved a low insertion loss of $0.015$ dB/cm and a $10$ dB reduction in crosstalk noise within $5$ GHz, resulting in a bandwidth $2.5\times$ as high as that of a standard microstriplines of the same footprint. Furthermore, a $5$ ns input pulse showed minimal distortion and a $0.13$ ns/cm propagation delay in our proposed interconnect. Critically, the thin oxide layer minimally impacted the heat dissipation of Si substrate, demonstrating a fourfold reduction in temperature compared to an FR4 substrate. These full-wave simulation-supported findings present a viable pathway for high-density, thermally efficient interconnects in advanced packaging. |
| title | Electrical and Thermal Performance Tuning of Spoof Plasmonic Interconnect |
| topic | Optics Applied Physics |
| url | https://arxiv.org/abs/2510.16698 |