ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine
Fuente:
arXiv
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Preprint |
| Veröffentlicht: |
2025
|
| Schlagworte: | |
| Online-Zugang: | |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| _version_ | 1866908827185577984 |
|---|---|
| author | Kumar, Sonu Nair, Arjun S. Chaudhary, Bhawna Lokhande, Mukul Vishvakarma, Santosh Kumar |
| author_facet | Kumar, Sonu Nair, Arjun S. Chaudhary, Bhawna Lokhande, Mukul Vishvakarma, Santosh Kumar |
| contents | We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN approaches, the proposed neuron leverages modular and performance-optimised CORDIC stages with a latency-area trade-off. We introduce a novel Constraint-Aware Modular Parallelism (CAMP) with Precision & Stability handling to leverage maximum speedup and utilisation of hardware through hardware software co-design. The FPGA implementation of the RCHH neuron shows 24.5% LUT reduction and 35.2% improved speed, compared to SoTA designs, with 70% better normalised root mean square error (NRMSE). Furthermore, the CNP exhibits 2.85x higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN engine, with only a 0.35% accuracy drop relative to the DNN counterpart on the MNIST dataset. The overall results indicate that the design shows biologically accurate, low-resource spiking neural network implementations for resource-constrained edge AI applications. The reproducibility codes are publicly available at https://github.com/mukullokhande99/CNP RCHH, facilitating rapid integration and further development by researchers. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_17392 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine Kumar, Sonu Nair, Arjun S. Chaudhary, Bhawna Lokhande, Mukul Vishvakarma, Santosh Kumar Neural and Evolutionary Computing Hardware Architecture We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN approaches, the proposed neuron leverages modular and performance-optimised CORDIC stages with a latency-area trade-off. We introduce a novel Constraint-Aware Modular Parallelism (CAMP) with Precision & Stability handling to leverage maximum speedup and utilisation of hardware through hardware software co-design. The FPGA implementation of the RCHH neuron shows 24.5% LUT reduction and 35.2% improved speed, compared to SoTA designs, with 70% better normalised root mean square error (NRMSE). Furthermore, the CNP exhibits 2.85x higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN engine, with only a 0.35% accuracy drop relative to the DNN counterpart on the MNIST dataset. The overall results indicate that the design shows biologically accurate, low-resource spiking neural network implementations for resource-constrained edge AI applications. The reproducibility codes are publicly available at https://github.com/mukullokhande99/CNP RCHH, facilitating rapid integration and further development by researchers. |
| title | ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine |
| topic | Neural and Evolutionary Computing Hardware Architecture |
| url | https://arxiv.org/abs/2510.17392 |