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QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

Fuente: arXiv

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Bibliographic Details
Main Authors:	Zhang, Yang, Zhang, Rui, Guo, Jiaming, Huang, Lei, Huang, Di, Zhao, Yunpu, Cheng, Shuyao, Jin, Pengwei, Li, Chongxiao, Du, Zidong, Hu, Xing, Guo, Qi, Chen, Yunji
Format:	Preprint
Published:	2025
Subjects:	Machine Learning Hardware Architecture Programming Languages
Online Access:	Acceder al recurso
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