RejSCore: Rejection Sampling Core for Multivariate-based Public key Cryptography
Fuente:
arXiv
Saved in:
| Main Authors: | Imran, Malik, Khan, Safiullah, Abideen, Zain Ul, Rafferty, Ciara, Khalid, Ayesha, Rashid, Muhammad, O'Neill, Maire |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025)
by: Malik, Arsalan Ali
Published: (2025)
Architectural Limits of Cloud TPUs in Finite-Field Cryptography
by: Dang, Hung, et al.
Published: (2026)
by: Dang, Hung, et al.
Published: (2026)
The Case for Persistent CXL switches
by: Hadi, Khan Shaikhul, et al.
Published: (2025)
by: Hadi, Khan Shaikhul, et al.
Published: (2025)
Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
by: Kumar, Aman, et al.
Published: (2024)
by: Kumar, Aman, et al.
Published: (2024)
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design
by: Pan, Tianwei, et al.
Published: (2025)
by: Pan, Tianwei, et al.
Published: (2025)
Driving Sustainable Development Goals: The Nexus Between Sustainability Performance and ESG Investment
by: Zain Ul Abideen
Published: (2025)
by: Zain Ul Abideen
Published: (2025)
The moderating role of investor sentiments between sustainability reporting and firm reputation. Evidence from Chinese listed firms
by: Zain Ul Abideen
Published: (2024)
by: Zain Ul Abideen
Published: (2024)
High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)
by: Amael, Joshua Tito, et al.
Published: (2024)
Understanding Simulated Architecture via gem5 Call-Stack Profiling
by: Söderström, Johan, et al.
Published: (2026)
by: Söderström, Johan, et al.
Published: (2026)
CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing
by: Zhang, Jingyao, et al.
Published: (2025)
by: Zhang, Jingyao, et al.
Published: (2025)
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
by: Liao, Yuchao, et al.
Published: (2026)
by: Liao, Yuchao, et al.
Published: (2026)
Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography
by: Baidya, Paresh, et al.
Published: (2025)
by: Baidya, Paresh, et al.
Published: (2025)
Efficient Layered New Bit-Flipping QC-MDPC Decoder for BIKE Post-Quantum Cryptography
by: Cai, Jiaxuan, et al.
Published: (2024)
by: Cai, Jiaxuan, et al.
Published: (2024)
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture
by: Baidya, Paresh, et al.
Published: (2022)
by: Baidya, Paresh, et al.
Published: (2022)
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography
by: Tan, Weihang, et al.
Published: (2021)
by: Tan, Weihang, et al.
Published: (2021)
ApproXAI: Energy-Efficient Hardware Acceleration of Explainable AI using Approximate Computing
by: Siddique, Ayesha, et al.
Published: (2025)
by: Siddique, Ayesha, et al.
Published: (2025)
RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)
by: Tan, Qinhan, et al.
Published: (2024)
Design of a GPU with Heterogeneous Cores for Graphics
by: Tomás, Aurora, et al.
Published: (2026)
by: Tomás, Aurora, et al.
Published: (2026)
Potential and Limitation of High-Frequency Cores and Caches
by: Pai, Kunal, et al.
Published: (2024)
by: Pai, Kunal, et al.
Published: (2024)
Accelerating Detailed Routing Convergence through Offline Reinforcement Learning
by: Khan, Afsara, et al.
Published: (2025)
by: Khan, Afsara, et al.
Published: (2025)
TRACE: Unlocking Effective CXL Bandwidth via Lossless Compression and Precision Scaling
by: Xie, Rui, et al.
Published: (2025)
by: Xie, Rui, et al.
Published: (2025)
Reimagining Memory Access for LLM Inference: Compression-Aware Memory Controller Design
by: Xie, Rui, et al.
Published: (2025)
by: Xie, Rui, et al.
Published: (2025)
L2R-CIPU: Efficient CNN Computation with Left-to-Right Composite Inner Product Units
by: Nisar, Malik Zohaib, et al.
Published: (2024)
by: Nisar, Malik Zohaib, et al.
Published: (2024)
Runtime Energy Monitoring for RISC-V Soft-Cores
by: Scionti, Alberto, et al.
Published: (2025)
by: Scionti, Alberto, et al.
Published: (2025)
Optimizing Energy Efficiency in Subthreshold RISC-V Cores
by: Djupdal, Asbjørn, et al.
Published: (2025)
by: Djupdal, Asbjørn, et al.
Published: (2025)
Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure
by: Xie, Rui, et al.
Published: (2025)
by: Xie, Rui, et al.
Published: (2025)
Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
by: Xie, Rui, et al.
Published: (2025)
by: Xie, Rui, et al.
Published: (2025)
Energy-Efficient QoS-Aware Scheduling for S-NUCA Many-Cores
by: Wasala, Sudam M., et al.
Published: (2025)
by: Wasala, Sudam M., et al.
Published: (2025)
Low Complexity Deep Learning Augmented Wireless Channel Estimation for Pilot-Based OFDM on Zynq System on Chip
by: Sharma, Animesh, et al.
Published: (2024)
by: Sharma, Animesh, et al.
Published: (2024)
Empirically-Calibrated H100 Node Power Models for Reducing Uncertainty in AI Training Energy Estimation
by: Newkirk, Alex C., et al.
Published: (2025)
by: Newkirk, Alex C., et al.
Published: (2025)
DSLR-CNN: Efficient CNN Acceleration using Digit-Serial Left-to-Right Arithmetic
by: Nisar, Malik Zohaib, et al.
Published: (2025)
by: Nisar, Malik Zohaib, et al.
Published: (2025)
Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification
by: Ikeda, Sosei, et al.
Published: (2025)
by: Ikeda, Sosei, et al.
Published: (2025)
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
by: Xue, Bing, et al.
Published: (2024)
by: Xue, Bing, et al.
Published: (2024)
NX-CGRA: A Programmable Hardware Accelerator for Core Transformer Algorithms on Edge Devices
by: Prasad, Rohit
Published: (2025)
by: Prasad, Rohit
Published: (2025)
Towards Efficient and Accurate Detection of On-Chip Fail-Slow Failures for Many-Core Accelerators
by: Wu, Junchi, et al.
Published: (2025)
by: Wu, Junchi, et al.
Published: (2025)
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
by: Tedeschi, Riccardo, et al.
Published: (2025)
by: Tedeschi, Riccardo, et al.
Published: (2025)
Empirical Measurements of AI Training Power Demand on a GPU-Accelerated Node
by: Latif, Imran, et al.
Published: (2024)
by: Latif, Imran, et al.
Published: (2024)
Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays
by: Siddique, Ayesha, et al.
Published: (2025)
by: Siddique, Ayesha, et al.
Published: (2025)
SONIQ: System-Optimized Noise-Injected Ultra-Low-Precision Quantization with Full-Precision Parity
by: Zhou, Cyrus, et al.
Published: (2023)
by: Zhou, Cyrus, et al.
Published: (2023)
Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores
by: Colagrande, Luca, et al.
Published: (2026)
by: Colagrande, Luca, et al.
Published: (2026)
Similar Items
-
Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application
by: Malik, Arsalan Ali
Published: (2025) -
Architectural Limits of Cloud TPUs in Finite-Field Cryptography
by: Dang, Hung, et al.
Published: (2026) -
The Case for Persistent CXL switches
by: Hadi, Khan Shaikhul, et al.
Published: (2025) -
Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
by: Kumar, Aman, et al.
Published: (2024) -
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design
by: Pan, Tianwei, et al.
Published: (2025)