Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908614053068800 |
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| author | Krishna, L. Hemanth Bodapati, Srinivasu Veeramachaneni, Sreehari Jammu, BhaskaraRao Sk, Noor Mahammad |
| author_facet | Krishna, L. Hemanth Bodapati, Srinivasu Veeramachaneni, Sreehari Jammu, BhaskaraRao Sk, Noor Mahammad |
| contents | This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_22674 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications Krishna, L. Hemanth Bodapati, Srinivasu Veeramachaneni, Sreehari Jammu, BhaskaraRao Sk, Noor Mahammad Hardware Architecture Information Theory Image and Video Processing This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications. |
| title | Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications |
| topic | Hardware Architecture Information Theory Image and Video Processing |
| url | https://arxiv.org/abs/2510.22674 |