Saved in:
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2510.24112 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866915815104708608 |
|---|---|
| author | Wu, Junchi Wan, Xinfei Li, Zhuoran Jin, Yuyang Sun, Guangyu Liang, Yun Zhou, Diyu Zhuo, Youwei |
| author_facet | Wu, Junchi Wan, Xinfei Li, Zhuoran Jin, Yuyang Sun, Guangyu Liang, Yun Zhou, Diyu Zhuo, Youwei |
| contents | Many-core accelerators are essential for high-performance deep learning, but their performance is undermined by widespread fail-slow failures. Detecting such failures on-chip is challenging, as prior methods from distributed systems are unsuitable due to strict memory limits and their inability to track failures across the hardware topology. This paper introduces SLOTH, a lightweight, hardware-aware framework for practical on-chip fail-slow detection in many-core accelerators. SLOTH combines workload-aware instrumentation for operator-level monitoring with minimal overhead, on-the-fly trace compression to operate within kilobytes of memory, and a novel topology-aware ranking algorithm to pinpoint a failure's root cause. We evaluate SLOTH on a wide range of representative DNN workloads. The results demonstrate that SLOTH reduces the storage overhead by an average of 115.9$\times$, while achieving an average fail-slow detection accuracy of 86.77% and a false positive rate (FPR) of 12.11%. More importantly, SLOTH scales effectively across different many-core accelerator architectures, making it practical for large-scale deployments. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_24112 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Towards Efficient and Accurate Detection of On-Chip Fail-Slow Failures for Many-Core Accelerators Wu, Junchi Wan, Xinfei Li, Zhuoran Jin, Yuyang Sun, Guangyu Liang, Yun Zhou, Diyu Zhuo, Youwei Hardware Architecture Many-core accelerators are essential for high-performance deep learning, but their performance is undermined by widespread fail-slow failures. Detecting such failures on-chip is challenging, as prior methods from distributed systems are unsuitable due to strict memory limits and their inability to track failures across the hardware topology. This paper introduces SLOTH, a lightweight, hardware-aware framework for practical on-chip fail-slow detection in many-core accelerators. SLOTH combines workload-aware instrumentation for operator-level monitoring with minimal overhead, on-the-fly trace compression to operate within kilobytes of memory, and a novel topology-aware ranking algorithm to pinpoint a failure's root cause. We evaluate SLOTH on a wide range of representative DNN workloads. The results demonstrate that SLOTH reduces the storage overhead by an average of 115.9$\times$, while achieving an average fail-slow detection accuracy of 86.77% and a false positive rate (FPR) of 12.11%. More importantly, SLOTH scales effectively across different many-core accelerator architectures, making it practical for large-scale deployments. |
| title | Towards Efficient and Accurate Detection of On-Chip Fail-Slow Failures for Many-Core Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2510.24112 |