Cover Image

Taming the Tail: NoI Topology Synthesis for Mixed DL Workloads on Chiplet-Based Accelerators

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Shukla, Arnav, Sharma, Harsh, Bharadwaj, Srikant, Abrol, Vinayak, Deb, Sujay
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence Machine Learning
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Chiplet-Based RISC-V SoC with Modular AI Acceleration
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)

THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures
by: Kanani, Alish, et al.
Published: (2025)

Mapping Space Exploration for Multi-Chiplet Accelerators Targeting LLM Inference Serving Workloads
by: Li, Boyu, et al.
Published: (2025)

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators
by: Das, Abhijit, et al.
Published: (2022)

Sangam: Chiplet-Based DRAM-PIM Accelerator with CXL Integration for LLM Inferencing
by: Kiyawat, Khyati, et al.
Published: (2025)

CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems
by: Pfromm, Lukas, et al.
Published: (2025)

Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning
by: Mishty, Kaniz, et al.
Published: (2024)

Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures enabled by Non-bendable Glass Interposer
by: Sharma, Harsh, et al.
Published: (2025)

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators
by: Vellaisamy, Prabhu, et al.
Published: (2026)

A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
by: Sharma, Harsh, et al.
Published: (2023)

FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
by: Iff, Patrick, et al.
Published: (2025)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
by: Iff, Patrick, et al.
Published: (2025)

Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
by: Sharma, Harsh, et al.
Published: (2024)

Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity
by: Qian, Chao, et al.
Published: (2024)

SLTarch: Towards Scalable Point-Based Neural Rendering by Taming Workload Imbalance and Memory Irregularity
by: Li, Xingyang, et al.
Published: (2025)

SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators
by: Odema, Mohanad, et al.
Published: (2024)

MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
by: Pfromm, Lukas, et al.
Published: (2024)

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
by: Ahmad, Adeel, et al.
Published: (2025)

Monad: Towards Cost-effective Specialization for Chiplet-based Spatial Accelerators
by: Hao, Xiaochen, et al.
Published: (2023)

Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization
by: Krestinskaya, Olga, et al.
Published: (2024)

Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles
by: Narashiman, Swathi, et al.
Published: (2024)

Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
by: Feng, Yinxiao, et al.
Published: (2022)

RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
by: Iff, Patrick, et al.
Published: (2023)

TurboAttention: Efficient Attention Approximation For High Throughputs LLMs
by: Kang, Hao, et al.
Published: (2024)

HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads
by: Negi, Shubham, et al.
Published: (2024)

Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation
by: Deng, Zhihui, et al.
Published: (2024)

PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration
by: Chong, Yue Jiet, et al.
Published: (2025)

CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure
by: Kim, Sangpyo, et al.
Published: (2023)

Mozart: A Chiplet Ecosystem-Accelerator Codesign Framework for Composable Bespoke Application Specific Integrated Circuits
by: Jin, Haoran, et al.
Published: (2025)

The Role of Advanced Computer Architectures in Accelerating Artificial Intelligence Workloads
by: Amin, Shahid, et al.
Published: (2025)

Link Quality Aware Pathfinding for Chiplet Interconnects
by: Yen, Aaron, et al.
Published: (2026)

The Survey of Chiplet-based Integrated Architecture: An EDA perspective
by: Chen, Shixin, et al.
Published: (2024)

Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators
by: Musavi, Mariam, et al.
Published: (2024)

Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
by: Yu, Zhongkai, et al.
Published: (2024)

ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification
by: Monfared, Saleh Khalaj, et al.
Published: (2025)

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
by: Scheffler, Paul, et al.
Published: (2025)

Hecaton: Training Large Language Models with Scalable Chiplet Systems
by: Huang, Zongle, et al.
Published: (2024)

MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator
by: Wang, Cong, et al.
Published: (2024)

M$^2$-ViT: Accelerating Hybrid Vision Transformers with Two-Level Mixed Quantization
by: Liang, Yanbiao, et al.
Published: (2024)

Messaging-based Adaptive Vector Computing (MAVeC) Accelerator for AI Workloads
by: Chowdhury, Md. Rownak Hossain, et al.
Published: (2024)