2D Canonical Approach for Beating the Boltzmann Tyranny Using Memory
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arXiv
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| Format: | Preprint |
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2025
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| author | Silva, Rafael Schio Wengenroth Pradhan, Soumen Hartmann, Fabian Castelano, Leonardo K. Lipan, Ovidiu Höfling, Sven Lopez-Richard, Victor |
| author_facet | Silva, Rafael Schio Wengenroth Pradhan, Soumen Hartmann, Fabian Castelano, Leonardo K. Lipan, Ovidiu Höfling, Sven Lopez-Richard, Victor |
| contents | The 60 mV$/$decade subthreshold limit at room temperature, coined as the Boltzmann tyranny, remains a fundamental obstacle to the continued down-scaling of conventional transistors. While several strategies have sought to overcome this constraint through non-thermal carrier injection, most rely on ferroelectric-based or otherwise material-specific mechanisms that require complex fabrication and stability control. Here, we develop a universal theoretical framework showing that intrinsic memory effects in nanometric field-effect transistors can naturally bypass this limit. Within the Landauer-Büttiker quantum transport formalism, we incorporate charge-trapping mechanisms that dynamically renormalize the conduction band edge. The resulting analytical expression for the subthreshold swing explicitly links memory dynamics to gate efficiency, revealing that a reduced carrier generation rate or enhanced trapping activity leads to sub-thermal switching, thus breaking the Boltzmann barrier. The model captures key experimental features and provides clear, generalizable design principles, establishing memory-assisted transistors as a robust pathway toward ultra-low-power and multifunctional electronic architectures. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_24883 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | 2D Canonical Approach for Beating the Boltzmann Tyranny Using Memory Silva, Rafael Schio Wengenroth Pradhan, Soumen Hartmann, Fabian Castelano, Leonardo K. Lipan, Ovidiu Höfling, Sven Lopez-Richard, Victor Applied Physics The 60 mV$/$decade subthreshold limit at room temperature, coined as the Boltzmann tyranny, remains a fundamental obstacle to the continued down-scaling of conventional transistors. While several strategies have sought to overcome this constraint through non-thermal carrier injection, most rely on ferroelectric-based or otherwise material-specific mechanisms that require complex fabrication and stability control. Here, we develop a universal theoretical framework showing that intrinsic memory effects in nanometric field-effect transistors can naturally bypass this limit. Within the Landauer-Büttiker quantum transport formalism, we incorporate charge-trapping mechanisms that dynamically renormalize the conduction band edge. The resulting analytical expression for the subthreshold swing explicitly links memory dynamics to gate efficiency, revealing that a reduced carrier generation rate or enhanced trapping activity leads to sub-thermal switching, thus breaking the Boltzmann barrier. The model captures key experimental features and provides clear, generalizable design principles, establishing memory-assisted transistors as a robust pathway toward ultra-low-power and multifunctional electronic architectures. |
| title | 2D Canonical Approach for Beating the Boltzmann Tyranny Using Memory |
| topic | Applied Physics |
| url | https://arxiv.org/abs/2510.24883 |