Platform Architecture for Tight Coupling of High-Performance Computing with Quantum Processors
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arXiv
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| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908624323870720 |
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| author | Caldwell, Shane A. Khazraee, Moein Agostini, Elena Lassiter, Tom Simpson, Corey Kahalon, Omri Kanuri, Mrudula Kim, Jin-Sung Stanwyck, Sam Li, Muyuan Olle, Jan Chamberland, Christopher Howe, Ben Schmitt, Bruno Lietz, Justin G. McCaskey, Alex Ye, Jun Li, Ang Magann, Alicia B. Ostrove, Corey I. Rudinger, Kenneth Blume-Kohout, Robin Young, Kevin Miller, Nathan E. Xu, Yilun Huang, Gang Siddiqi, Irfan Lange, John Zimmer, Christopher Humble, Travis |
| author_facet | Caldwell, Shane A. Khazraee, Moein Agostini, Elena Lassiter, Tom Simpson, Corey Kahalon, Omri Kanuri, Mrudula Kim, Jin-Sung Stanwyck, Sam Li, Muyuan Olle, Jan Chamberland, Christopher Howe, Ben Schmitt, Bruno Lietz, Justin G. McCaskey, Alex Ye, Jun Li, Ang Magann, Alicia B. Ostrove, Corey I. Rudinger, Kenneth Blume-Kohout, Robin Young, Kevin Miller, Nathan E. Xu, Yilun Huang, Gang Siddiqi, Irfan Lange, John Zimmer, Christopher Humble, Travis |
| contents | We propose an architecture, called NVQLink, for connecting high-performance computing (HPC) resources to the control system of a quantum processing unit (QPU) to accelerate workloads necessary to the operation of the QPU. We aim to support every physical modality of QPU and every type of QPU system controller (QSC). The HPC resource is optimized for real-time (latency-bounded) processing on tasks with latency tolerances of tens of microseconds. The network connecting the HPC and QSC is implemented on commercially available Ethernet and can be adopted relatively easily by QPU and QSC builders, and we report a round-trip latency measurement of 3.96 microseconds (max) with prospects of further optimization. We describe an extension to the CUDA-Q programming model and runtime architecture to support real-time callbacks and data marshaling between the HPC and QSC. By doing so, NVQLink extends heterogeneous, kernel-based programming to the QSC, allowing the programmer to address CPU, GPU, and FPGA subsystems in the QSC, all in the same C++ program, avoiding the use of a performance-limiting HTTP interface. We provide a pattern for QSC builders to integrate with this architecture by making use of multi-level intermediate representation dialects and progressive lowering to encapsulate QSC code. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_25213 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Platform Architecture for Tight Coupling of High-Performance Computing with Quantum Processors Caldwell, Shane A. Khazraee, Moein Agostini, Elena Lassiter, Tom Simpson, Corey Kahalon, Omri Kanuri, Mrudula Kim, Jin-Sung Stanwyck, Sam Li, Muyuan Olle, Jan Chamberland, Christopher Howe, Ben Schmitt, Bruno Lietz, Justin G. McCaskey, Alex Ye, Jun Li, Ang Magann, Alicia B. Ostrove, Corey I. Rudinger, Kenneth Blume-Kohout, Robin Young, Kevin Miller, Nathan E. Xu, Yilun Huang, Gang Siddiqi, Irfan Lange, John Zimmer, Christopher Humble, Travis Quantum Physics We propose an architecture, called NVQLink, for connecting high-performance computing (HPC) resources to the control system of a quantum processing unit (QPU) to accelerate workloads necessary to the operation of the QPU. We aim to support every physical modality of QPU and every type of QPU system controller (QSC). The HPC resource is optimized for real-time (latency-bounded) processing on tasks with latency tolerances of tens of microseconds. The network connecting the HPC and QSC is implemented on commercially available Ethernet and can be adopted relatively easily by QPU and QSC builders, and we report a round-trip latency measurement of 3.96 microseconds (max) with prospects of further optimization. We describe an extension to the CUDA-Q programming model and runtime architecture to support real-time callbacks and data marshaling between the HPC and QSC. By doing so, NVQLink extends heterogeneous, kernel-based programming to the QSC, allowing the programmer to address CPU, GPU, and FPGA subsystems in the QSC, all in the same C++ program, avoiding the use of a performance-limiting HTTP interface. We provide a pattern for QSC builders to integrate with this architecture by making use of multi-level intermediate representation dialects and progressive lowering to encapsulate QSC code. |
| title | Platform Architecture for Tight Coupling of High-Performance Computing with Quantum Processors |
| topic | Quantum Physics |
| url | https://arxiv.org/abs/2510.25213 |