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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2510.25958 |
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| _version_ | 1866911240315469824 |
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| author | Pfromm, Lukas Kanani, Alish Sharma, Harsh Doppa, Janardhan Rao Pande, Partha Pratim Ogras, Umit Y. |
| author_facet | Pfromm, Lukas Kanani, Alish Sharma, Harsh Doppa, Janardhan Rao Pande, Partha Pratim Ogras, Umit Y. |
| contents | Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework's versatility, up to 340% accuracy improvement, and power/thermal analysis capability. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2510_25958 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems Pfromm, Lukas Kanani, Alish Sharma, Harsh Doppa, Janardhan Rao Pande, Partha Pratim Ogras, Umit Y. Hardware Architecture Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework's versatility, up to 340% accuracy improvement, and power/thermal analysis capability. |
| title | CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2510.25958 |