FeNN-DMA: A RISC-V SoC for SNN acceleration
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arXiv
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| Auteurs principaux: | , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866908817053188096 |
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| author | Aizaz, Zainab Knight, James C. Nowotny, Thomas |
| author_facet | Aizaz, Zainab Knight, James C. Nowotny, Thomas |
| contents | Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays (FPGAs) are designed for such memory-bound workloads, and here we present a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs. We show that FeNN-DMA has comparable resource usage and energy requirements to state-of-the-art fixed-function SNN accelerators, yet it supports more complex neuron models and network topologies, and can simulate up to 16 thousand neurons and 256 million synapses per core. Using this functionality, we demonstrate state-of-the-art classification accuracy on the Spiking Heidelberg Digits, Neuromorphic MNIST and Braille tactile classification tasks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_00732 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | FeNN-DMA: A RISC-V SoC for SNN acceleration Aizaz, Zainab Knight, James C. Nowotny, Thomas Neural and Evolutionary Computing Artificial Intelligence Hardware Architecture Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays (FPGAs) are designed for such memory-bound workloads, and here we present a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs. We show that FeNN-DMA has comparable resource usage and energy requirements to state-of-the-art fixed-function SNN accelerators, yet it supports more complex neuron models and network topologies, and can simulate up to 16 thousand neurons and 256 million synapses per core. Using this functionality, we demonstrate state-of-the-art classification accuracy on the Spiking Heidelberg Digits, Neuromorphic MNIST and Braille tactile classification tasks. |
| title | FeNN-DMA: A RISC-V SoC for SNN acceleration |
| topic | Neural and Evolutionary Computing Artificial Intelligence Hardware Architecture |
| url | https://arxiv.org/abs/2511.00732 |