Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories
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arXiv
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| Main Authors: | , , , , , , , , , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866915592240365568 |
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| author | Athena, Fabia F. Hartanto, Jonathan Passlack, Matthias Evans, Jack C. Qin, Jimmy Dede, Didem Jana, Koustav Liu, Shuhan Peña, Tara Pop, Eric Pitner, Greg Radu, Iuliana P. McIntyre, Paul C. Wong, H. -S. Philip |
| author_facet | Athena, Fabia F. Hartanto, Jonathan Passlack, Matthias Evans, Jack C. Qin, Jimmy Dede, Didem Jana, Koustav Liu, Shuhan Peña, Tara Pop, Eric Pitner, Greg Radu, Iuliana P. McIntyre, Paul C. Wong, H. -S. Philip |
| contents | We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_00786 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories Athena, Fabia F. Hartanto, Jonathan Passlack, Matthias Evans, Jack C. Qin, Jimmy Dede, Didem Jana, Koustav Liu, Shuhan Peña, Tara Pop, Eric Pitner, Greg Radu, Iuliana P. McIntyre, Paul C. Wong, H. -S. Philip Materials Science Mesoscale and Nanoscale Physics Applied Physics We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption. |
| title | Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories |
| topic | Materials Science Mesoscale and Nanoscale Physics Applied Physics |
| url | https://arxiv.org/abs/2511.00786 |