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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2511.03203 |
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| _version_ | 1866918189894467584 |
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| author | Yu, Deyang Liu, Chenchen Zhang, Chuanjie Fang, Xiao Zhao, Weisheng |
| author_facet | Yu, Deyang Liu, Chenchen Zhang, Chuanjie Fang, Xiao Zhao, Weisheng |
| contents | The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit- Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is (en) decoded as spikes using lightweight circuits, eliminating the need for conventional area- and powerintensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_03203 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM Yu, Deyang Liu, Chenchen Zhang, Chuanjie Fang, Xiao Zhao, Weisheng Hardware Architecture The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit- Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is (en) decoded as spikes using lightweight circuits, eliminating the need for conventional area- and powerintensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs. |
| title | An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2511.03203 |