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| Auteurs principaux: | , , , , , , , , , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| Accès en ligne: | https://arxiv.org/abs/2511.04321 |
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| _version_ | 1866908633327992832 |
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| author | Zhang, Yuanpeng Hu, Xing Chen, Xi Yuan, Zhihang Li, Cong Zhu, Jingchen Wang, Zhao Zhang, Chenguang Si, Xin Gao, Wei Wu, Qiang Wang, Runsheng Sun, Guangyu |
| author_facet | Zhang, Yuanpeng Hu, Xing Chen, Xi Yuan, Zhihang Li, Cong Zhu, Jingchen Wang, Zhao Zhang, Chenguang Si, Xin Gao, Wei Wu, Qiang Wang, Runsheng Sun, Guangyu |
| contents | SRAM Processing-in-Memory (PIM) has emerged as the most promising implementation for high-performance PIM, delivering superior computing density, energy efficiency, and computational precision. However, the pursuit of higher performance necessitates more complex circuit designs and increased operating frequencies, which exacerbate IR-drop issues. Severe IR-drop can significantly degrade chip performance and even threaten reliability. Conventional circuit-level IR-drop mitigation methods, such as back-end optimizations, are resource-intensive and often compromise power, performance, and area (PPA). To address these challenges, we propose AIM, comprehensive software and hardware co-design for architecture-level IR-drop mitigation in high-performance PIM. Initially, leveraging the bit-serial and in-situ dataflow processing properties of PIM, we introduce Rtog and HR, which establish a direct correlation between PIM workloads and IR-drop. Building on this foundation, we propose LHR and WDS, enabling extensive exploration of architecture-level IR-drop mitigation while maintaining computational accuracy through software optimization. Subsequently, we develop IR-Booster, a dynamic adjustment mechanism that integrates software-level HR information with hardware-based IR-drop monitoring to adapt the V-f pairs of the PIM macro, achieving enhanced energy efficiency and performance. Finally, we propose the HR-aware task mapping method, bridging software and hardware designs to achieve optimal improvement. Post-layout simulation results on a 7nm 256-TOPS PIM chip demonstrate that AIM achieves up to 69.2% IR-drop mitigation, resulting in 2.29x energy efficiency improvement and 1.152x speedup. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_04321 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM Zhang, Yuanpeng Hu, Xing Chen, Xi Yuan, Zhihang Li, Cong Zhu, Jingchen Wang, Zhao Zhang, Chenguang Si, Xin Gao, Wei Wu, Qiang Wang, Runsheng Sun, Guangyu Hardware Architecture Artificial Intelligence Machine Learning SRAM Processing-in-Memory (PIM) has emerged as the most promising implementation for high-performance PIM, delivering superior computing density, energy efficiency, and computational precision. However, the pursuit of higher performance necessitates more complex circuit designs and increased operating frequencies, which exacerbate IR-drop issues. Severe IR-drop can significantly degrade chip performance and even threaten reliability. Conventional circuit-level IR-drop mitigation methods, such as back-end optimizations, are resource-intensive and often compromise power, performance, and area (PPA). To address these challenges, we propose AIM, comprehensive software and hardware co-design for architecture-level IR-drop mitigation in high-performance PIM. Initially, leveraging the bit-serial and in-situ dataflow processing properties of PIM, we introduce Rtog and HR, which establish a direct correlation between PIM workloads and IR-drop. Building on this foundation, we propose LHR and WDS, enabling extensive exploration of architecture-level IR-drop mitigation while maintaining computational accuracy through software optimization. Subsequently, we develop IR-Booster, a dynamic adjustment mechanism that integrates software-level HR information with hardware-based IR-drop monitoring to adapt the V-f pairs of the PIM macro, achieving enhanced energy efficiency and performance. Finally, we propose the HR-aware task mapping method, bridging software and hardware designs to achieve optimal improvement. Post-layout simulation results on a 7nm 256-TOPS PIM chip demonstrate that AIM achieves up to 69.2% IR-drop mitigation, resulting in 2.29x energy efficiency improvement and 1.152x speedup. |
| title | AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM |
| topic | Hardware Architecture Artificial Intelligence Machine Learning |
| url | https://arxiv.org/abs/2511.04321 |