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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2511.05321 |
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| _version_ | 1866908851592232960 |
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| author | Kirschner, Maximilian Dudzik, Konstantin Krusekamp, Ben Becker, Jürgen |
| author_facet | Kirschner, Maximilian Dudzik, Konstantin Krusekamp, Ben Becker, Jürgen |
| contents | Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. We present a new hardware architecture to bridge this gap between performance and predictability. The architecture features a multi-core vector processor with predictable cores, each equipped with local scratchpad memories. A central management core orchestrates access to shared external memory following a statically determined schedule. To evaluate the proposed hardware architecture, we analyze different variants of our parameterized design. We compare these variants to a baseline architecture consisting of a single-core vector processor with large vector registers. We find that configurations with a larger number of smaller cores achieve better performance due to increased effective memory bandwidth and higher clock frequencies. Crucially for real-time systems, execution time fluctuation remains very low, demonstrating the platform's time predictability. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_05321 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference Kirschner, Maximilian Dudzik, Konstantin Krusekamp, Ben Becker, Jürgen Hardware Architecture Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. We present a new hardware architecture to bridge this gap between performance and predictability. The architecture features a multi-core vector processor with predictable cores, each equipped with local scratchpad memories. A central management core orchestrates access to shared external memory following a statically determined schedule. To evaluate the proposed hardware architecture, we analyze different variants of our parameterized design. We compare these variants to a baseline architecture consisting of a single-core vector processor with large vector registers. We find that configurations with a larger number of smaller cores achieve better performance due to increased effective memory bandwidth and higher clock frequencies. Crucially for real-time systems, execution time fluctuation remains very low, demonstrating the platform's time predictability. |
| title | MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2511.05321 |