EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations
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arXiv
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| Hauptverfasser: | , |
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| Format: | Preprint |
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2025
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| _version_ | 1866912697867567104 |
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| author | Choi, Sangun Oh, Yunho |
| author_facet | Choi, Sangun Oh, Yunho |
| contents | Embedding vector operations are a key component of modern deep neural network workloads. Unlike matrix operations with deterministic access patterns, embedding vector operations exhibit input data-dependent and non-deterministic memory accesses. Existing neural processing unit (NPU) simulators focus on matrix computations with simple double-buffered on-chip memory systems, lacking the modeling capability for realistic embedding behavior. Next-generation NPUs, however, call for more flexible on-chip memory architectures that can support diverse access and management schemes required by embedding workloads. To enable flexible exploration and design of emerging NPU architectures, we present EONSim, an NPU simulator that holistically models both matrix and embedding vector operations. EONSim integrates a validated performance model for matrix computations with detailed memory simulation for embedding accesses, supporting various on-chip memory management policies. Validated against TPUv6e, EONSim achieves an average inference time error of 1.4\% and an average on-chip memory access count error of 2.2\%. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_06679 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations Choi, Sangun Oh, Yunho Hardware Architecture Embedding vector operations are a key component of modern deep neural network workloads. Unlike matrix operations with deterministic access patterns, embedding vector operations exhibit input data-dependent and non-deterministic memory accesses. Existing neural processing unit (NPU) simulators focus on matrix computations with simple double-buffered on-chip memory systems, lacking the modeling capability for realistic embedding behavior. Next-generation NPUs, however, call for more flexible on-chip memory architectures that can support diverse access and management schemes required by embedding workloads. To enable flexible exploration and design of emerging NPU architectures, we present EONSim, an NPU simulator that holistically models both matrix and embedding vector operations. EONSim integrates a validated performance model for matrix computations with detailed memory simulation for embedding accesses, supporting various on-chip memory management policies. Validated against TPUv6e, EONSim achieves an average inference time error of 1.4\% and an average on-chip memory access count error of 2.2\%. |
| title | EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2511.06679 |