:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Ma, Ruiyang, Zhou, Yunhao, Wang, Yipeng, Liu, Yi, Shi, Zhengyuan, Zheng, Ziyang, Chen, Kexin, He, Zhiqiang, Yan, Lingwei, Chen, Gang, Xu, Qiang, Luo, Guojie
Format:	Preprint
Published:	2025
Subjects:	Machine Learning
Online Access:	https://arxiv.org/abs/2511.09593
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

DeepRTL2: A Versatile Model for RTL-Related Tasks
by: Liu, Yi, et al.
Published: (2025)

DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model
by: Liu, Yi, et al.
Published: (2025)

DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis
by: Li, Zeju, et al.
Published: (2025)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)

CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
by: Shi, Zhengyuan, et al.
Published: (2026)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)

DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations
by: Khan, Sadaf, et al.
Published: (2024)

IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
by: Chen, Luanrong, et al.
Published: (2026)

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
by: Wang, Jing, et al.
Published: (2026)

RTL++: Graph-enhanced LLM for RTL Code Generation
by: Akyash, Mohammad, et al.
Published: (2025)

DeepGate3: Towards Scalable Circuit Representation Learning
by: Shi, Zhengyuan, et al.
Published: (2024)

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)

Alignment Unlocks Complementarity: A Framework for Multiview Circuit Representation Learning
by: Shi, Zhengyuan, et al.
Published: (2025)

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)

ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)

Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning
by: Liu, Yi, et al.
Published: (2025)

DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale
by: Zheng, Ziyang, et al.
Published: (2025)

Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities
by: Zhu, Jiaying, et al.
Published: (2025)

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
by: Akyash, Mohammad, et al.
Published: (2025)

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)

MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generation
by: Mashnoor, Nowfel, et al.
Published: (2026)

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
by: Liu, Shang, et al.
Published: (2025)

DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning
by: Shi, Zhengyuan, et al.
Published: (2025)

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)

RTLSquad: Multi-Agent Based Interpretable RTL Design
by: Wang, Bowei, et al.
Published: (2025)

GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)

SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning
by: Wang, Yiting, et al.
Published: (2025)

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
by: Wang, Yiting, et al.
Published: (2025)

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
by: Yao, Xufeng, et al.
Published: (2024)

CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
by: Mashnoor, Nowfel, et al.
Published: (2025)

R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII
by: Zhou, Zewei, et al.
Published: (2026)

RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)

Automated Multi-Agent Workflows for RTL Design
by: Bhattaram, Amulya, et al.
Published: (2025)

Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)

Parendi: Thousand-Way Parallel RTL Simulation
by: Emami, Mahyar, et al.
Published: (2024)

INSTILLER: Towards Efficient and Realistic RTL Fuzzing
by: Zhang, Gen, et al.
Published: (2024)

From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
by: Mashnoor, Nowfel, et al.
Published: (2026)

RTLocating: Intent-aware RTL Localization for Hardware Design Iteration
by: Xing, Changwen, et al.
Published: (2026)