Cover Image

Combined power management and congestion control in High-Speed Ethernet-based Networks for Supercomputers and Data Centers

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	de la Rosa, Miguel Sánchez, andújar, Francisco J., Escudero-Sahuquillo, Jesus, Sánchez, José L., Alfaro-Cortés, Francisco J.
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

On the Power Saving in High-Speed Ethernet-based Networks for Supercomputers and Data Centers
by: de la Rosa, Miguel Sánchez, et al.
Published: (2025)

On the Impact of Intra-node Communication in the Performance of Supercomputer and Data Center Interconnection Networks
by: Tarraga-Moreno, Joaquin, et al.
Published: (2025)

Characterization of Real Communication Patterns and Congestion Dynamics in HPC Interconnection Networks
by: de La Rosa, Miguel Sánchez, et al.
Published: (2026)

Scalable and Efficient Intra- and Inter-node Interconnection Networks for Post-Exascale Supercomputers and Data centers
by: Tarraga-Moreno, Joaquin, et al.
Published: (2025)

Improving Injection-Throttling Mechanisms for Congestion Control for Data-center and Supercomputer Interconnects
by: Olmedilla, Cristina, et al.
Published: (2025)

A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems
by: Liang, Chaoqun, et al.
Published: (2024)

Configurable Multi-Port Memory Architecture for High-Speed Data Communication
by: Dhakad, Narendra Singh, et al.
Published: (2024)

Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models
by: Peng, Huwan, et al.
Published: (2023)

AXON: An Automated Netlist Optimization Framework for High-Speed Adders
by: Yang, Tiantian, et al.
Published: (2026)

Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations
by: Mohammad, Sakib, et al.
Published: (2024)

Data-Rate-Aware High-Speed CNN Inference on FPGAs
by: Habermann, Tobias, et al.
Published: (2026)

FastFlow in FPGA Stacks of Data Centers
by: Paul, Rourab, et al.
Published: (2024)

Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge
by: Han, Zhaoyang, et al.
Published: (2024)

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device
by: Fu, Siqing, et al.
Published: (2023)

Improving dynamic congestion isolation in data-center networks
by: Merino, Alberto, et al.
Published: (2025)

An opportunity to improve Data Center Efficiency: Optimizing the Server's Upgrade Cycle
by: Nikolaou, Panagiota, et al.
Published: (2025)

Coyote v2: Raising the Level of Abstraction for Data Center FPGAs
by: Ramhorst, Benjamin, et al.
Published: (2025)

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis
by: Devadze, Sergei, et al.
Published: (2024)

FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar
by: Zyla, Klajd, et al.
Published: (2024)

Best Practices for Large Load Interconnections: A North American Perspective on Data Centers
by: Zahedi, Rafi, et al.
Published: (2026)

A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
by: Galimberti, Andrea, et al.
Published: (2025)

A methodology to automatically optimize dynamic memory managers applying grammatical evolution
by: Risco-Martín, José L., et al.
Published: (2024)

OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
by: Sarkar, Rishov, et al.
Published: (2025)

SpeedLLM: An FPGA Co-design of Large Language Model Inference Accelerator
by: Wang, Peipei, et al.
Published: (2025)

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators
by: Xue, Chenhao, et al.
Published: (2025)

RoCE BALBOA: Service-enhanced Data Center RDMA for SmartNICs
by: Heer, Maximilian Jakob, et al.
Published: (2025)

Disaggregated Architectures and the Redesign of Data Center Ecosystems: Scheduling, Pooling, and Infrastructure Trade-offs
by: Guo, Chao, et al.
Published: (2025)

DFabric: Scaling Out Data Parallel Applications with CXL-Ethernet Hybrid Interconnects
by: Zhang, Xu, et al.
Published: (2024)

Ultra Ethernet's Design Principles and Architectural Innovations
by: Hoefler, Torsten, et al.
Published: (2025)

Offloading Data Center Tax
by: Revankar, Akshay, et al.
Published: (2025)

Designing Approximate Arithmetic Circuits with Combined Error Constraints
by: Češka, Milan, et al.
Published: (2022)

Combining Power and Arithmetic Optimization via Datapath Rewriting
by: Coward, Samuel, et al.
Published: (2024)

Soft Error Probability Estimation of Nano-scale Combinational Circuits
by: Jockar, Ali, et al.
Published: (2025)

FastMamba: A High-Speed and Efficient Mamba Accelerator on FPGA with Accurate Quantization
by: Wang, Aotao, et al.
Published: (2025)

Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator
by: Belda, María José, et al.
Published: (2024)

PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine
by: Aliyev, Ilkin, et al.
Published: (2024)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
by: Cammarata, Danilo, et al.
Published: (2025)

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
by: Leon, Vasileios, et al.
Published: (2025)

A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design
by: Liu, Bingyang, et al.
Published: (2024)