Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity
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arXiv
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| Auteurs principaux: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866915636324597760 |
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| author | Haque, Emad Nalla, Pragnya Sudershan Zhang, Jeff Sapatnekar, Sachin S. Chakrabarti, Chaitali Cao, Yu |
| author_facet | Haque, Emad Nalla, Pragnya Sudershan Zhang, Jeff Sapatnekar, Sachin S. Chakrabarti, Chaitali Cao, Yu |
| contents | The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional input/output (I/O) circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and simulation program with integrated circuit emphasis (SPICE) simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2511_10760 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity Haque, Emad Nalla, Pragnya Sudershan Zhang, Jeff Sapatnekar, Sachin S. Chakrabarti, Chaitali Cao, Yu Hardware Architecture The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional input/output (I/O) circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and simulation program with integrated circuit emphasis (SPICE) simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets. |
| title | Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2511.10760 |