:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Kadiyala, Divya Kiran, Daglis, Alexandros
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2511.12349
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

IBEX: Internal Bandwidth-Efficient Compression Architecture for Scalable CXL Memory Expansion
by: Ko, Younghoon, et al.
Published: (2026)

CXL-GPU: Pushing GPU Memory Boundaries with the Integration of CXL Technologies
by: Gouk, Donghyun, et al.
Published: (2025)

TRACE: Unlocking Effective CXL Bandwidth via Lossless Compression and Precision Scaling
by: Xie, Rui, et al.
Published: (2025)

Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGA
by: Li, Jindong, et al.
Published: (2025)

Scaling Routers with In-Package Optics and High-Bandwidth Memories
by: Keslassy, Isaac, et al.
Published: (2026)

Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design
by: Liu, Qunyou, et al.
Published: (2026)

Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory
by: Hong, Jeongmin, et al.
Published: (2024)

Architectural and System Implications of CXL-enabled Tiered Memory
by: Yang, Yujie, et al.
Published: (2025)

Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
by: Sullivan, Connor Rudy, et al.
Published: (2026)

ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM
by: Zuepke, Alexander, et al.
Published: (2026)

Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators
by: Wang, Ruibao, et al.
Published: (2024)

Ecco: Improving Memory Bandwidth and Capacity for LLMs via Entropy-aware Cache Compression
by: Cheng, Feng, et al.
Published: (2025)

An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
by: Ferry, Corentin, et al.
Published: (2024)

H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory
by: Doumet, Mario, et al.
Published: (2024)

Octopus: Enhancing CXL Memory Pods via Sparse Topology
by: Zhong, Yuhong, et al.
Published: (2025)

Enabling Efficient Transaction Processing on CXL-Based Memory Sharing
by: Wang, Zhao, et al.
Published: (2025)

LMB: Augmenting PCIe Devices with CXL-Linked Memory Buffer
by: Wang, Jiapin, et al.
Published: (2024)

Prefill vs. Decode Bottlenecks: SRAM-Frequency Tradeoffs and the Memory-Bandwidth Ceiling
by: Atmer, Hannah, et al.
Published: (2025)

On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
by: Elahi, Mehdi, et al.
Published: (2025)

Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems
by: Sullivan, Connor, et al.
Published: (2024)

CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation
by: Wang, Yanjing, et al.
Published: (2024)

Fat-Tree QRAM: A High-Bandwidth Shared Quantum Random Access Memory for Parallel Queries
by: Xu, Shifan, et al.
Published: (2025)

Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
by: Olgun, Ataberk, et al.
Published: (2023)

Performance Characterizations and Usage Guidelines of Samsung CXL Memory Module Hybrid Prototype
by: Zeng, Jianping, et al.
Published: (2025)

A Full-System Simulation Framework for CXL-Based SSD Memory System
by: Wang, Yaohui, et al.
Published: (2025)

NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
by: Zhou, Zhe, et al.
Published: (2024)

Low-overhead General-purpose Near-Data Processing in CXL Memory Expanders
by: Ham, Hyungkyu, et al.
Published: (2024)

ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
by: Chen, Hanqiu, et al.
Published: (2024)

Tasa: Thermal-aware 3D-Stacked Architecture Design with Bandwidth Sharing for LLM Inference
by: He, Siyuan, et al.
Published: (2025)

FPGA-based Emulation and Device-Side Management for CXL-based Memory Tiering Systems
by: Chen, Yiqi, et al.
Published: (2025)

From Block to Byte: Transforming PCIe SSDs with CXL Memory Protocol and Instruction Annotation
by: Kwon, Miryeong, et al.
Published: (2025)

Cosmos: A CXL-Based Full In-Memory System for Approximate Nearest Neighbor Search
by: Ko, Seoyoung, et al.
Published: (2025)

The Case for Persistent CXL switches
by: Hadi, Khan Shaikhul, et al.
Published: (2025)

SkyByte: Architecting an Efficient Memory-Semantic CXL-based SSD with OS and Hardware Co-design
by: Zhang, Haoyang, et al.
Published: (2025)

DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation
by: Shao, Kunming, et al.
Published: (2025)

Toleo: Scaling Freshness to Tera-scale Memory using CXL and PIM
by: Dong, Juechu, et al.
Published: (2024)

CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
by: Goswami, Kaustav, et al.
Published: (2026)

ROSGuard: A Bandwidth Regulation Mechanism for ROS2-based Applications
by: Puente, Jon Altonaga, et al.
Published: (2025)

BOLT: Bandwidth-Optimized Lightning-Fast Oblivious Map powered by Secure HBM Accelerators
by: Guo, Yitong, et al.
Published: (2025)

CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device
by: Lin, Ye, et al.
Published: (2026)